Search results for "Masahiro Fujita"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yasuyuki Kimura, Fabrice G. Siméon, Sami S. Zoghbi, Yi Zhang, Jun Hatazawa, Victor W. Pike, Robert B. Innis, Masahiro Fujita	Quantification of metabotropic glutamate subtype 5 receptors in the brain by an equilibrium method using 18F-SP203.	NeuroImage	2012	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	Transaction-based post-silicon debug of many-core System-on-Chips.	ISQED	2012	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hiroaki Yoshida	Post-silicon patching for verification/debugging with high-level models and programmable logic.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita	Automated data analysis techniques for a modern silicon debug environment.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita	On error tolerance and Engineering Change with Partially Programmable Circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hiroaki Yoshida	Post-silicon debugging targeting electrical errors with patchable controllers (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita	Multi-Level Bounded Model Checking with Symbolic Counterexamples.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita	An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Elise Luong, Ronald Boellaard, Robert L. Gladding, Victor W. Pike, Robert B. Innis, Masahiro Fujita	Kinetic analysis in human brain of [11C](R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function.	NeuroImage	2011	DBLP DOI BibTeX RDF
1	Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita	SEU tolerant SRAM cell.	ISQED	2011	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques.	ISQED	2011	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	Global transaction ordering in Network-on-Chips for post-silicon validation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan	Client-tier Validation of Dynamic Web Applications.	ICSOFT	2011	DBLP BibTeX RDF
1	Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia	EFSM-based model-driven approach to concolic testing of system-level design.	MEMOCODE	2011	DBLP DOI BibTeX RDF
1	Masahiro Fujita	High Level Verification and Its Use at Pos-Silicon Debugging and Patching.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy	Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture.	FPT	2011	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols.	ATVA	2011	DBLP DOI BibTeX RDF
1	Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita	Optimization of Assertion Placement in Time-Constrained Embedded Systems.	European Test Symposium	2011	DBLP DOI BibTeX RDF	time-constrained embedded systems, soft errors, executable assertions
1	Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita	On-chip dynamic signal sequence slicing for efficient post-silicon debugging.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Utilizing high level design information to speed up post-silicon debugging.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Early case splitting and false path detection to improve high level ATPG techniques.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan	Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.	ARC	2011	DBLP DOI BibTeX RDF
1	Virendra Singh, Masahiro Fujita	Tutorial: "Post silicon debug of SOC designs".	SoCC	2011	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Masahiro Fujita	An energy-efficient patchable accelerator for post-silicon engineering changes.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita	Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Modular Datapath Optimization and Verification Based on Modular-HED.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Masahiro Fujita	Performance-Constrained Transistor Sizing for Different Cell Count Minimization.	JIP	2010	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto	Synthesis and formal verification of on-chip protocol transducers through decomposed specification.	ISQED	2010	DBLP DOI BibTeX RDF
1	Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita	SEU tolerant SRAM for FPGA applications.	FPT	2010	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	A debugging method for repairing post-silicon bugs of high performance processors in the fields.	FPT	2010	DBLP DOI BibTeX RDF
1	Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita	Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.	CASES	2010	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Guided gate-level ATPG for sequential circuits using a high-level test generation approach.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
1	Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita	Pipelined Microprocessors Optimization and Debugging.	ARC	2010	DBLP DOI BibTeX RDF
1	Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler	Polynomial datapath optimization using constraint solving and formal modelling.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita	Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.	ICCD	2010	DBLP DOI BibTeX RDF
1	Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita	Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita	Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	A Unified Framework for Equivalence Verification of Datapath Oriented Applications.	IEICE Transactions	2009	DBLP BibTeX RDF
1	O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita	A Formal Approach for Debugging Arithmetic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard	Functional Equivalence Verification Tools in High-Level Synthesis Flows.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents.	Autonomous Agents and Multi-Agent Systems	2009	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Masahiro Fujita	Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences.	ISQED	2009	DBLP DOI BibTeX RDF
1	O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita	High-level optimization of integer multipliers over a finite bit-width with verification capabilities.	MEMOCODE	2009	DBLP DOI BibTeX RDF
1	Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita	A Post-Silicon Debug Support Using High-Level Design Description.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Modular arithmetic decision procedure with auto-correction mechanism.	HLDVT	2009	DBLP DOI BibTeX RDF
1	O. Sarbishei, Bijan Alizadeh, Masahiro Fujita	Polynomial datapath optimization using partitioning and compensation heuristics.	DAC	2009	DBLP DOI BibTeX RDF	modular HED, polynomial datapath, high-level synthesis
1	Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi	Debugging from high level down to gate level.	DAC	2009	DBLP DOI BibTeX RDF	post-silicon debug, dependence analysis, system level design, equivalence checking, high-level design
1	Bijan Alizadeh, Masahiro Fujita	Improved heuristics for finite word-length polynomial datapath optimization.	ICCAD	2009	DBLP BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	Transaction-based debugging of system-on-chips with patterns.	ICCD	2009	DBLP DOI BibTeX RDF
1	Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita	3D Perception and Environment Map Generation for Humanoid Robot Navigation.	I. J. Robotic Res.	2008	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak	Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.	JSAT	2008	DBLP BibTeX RDF
1	Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida	A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams.	ICSOFT (SE/MUSE/GSDCA)	2008	DBLP BibTeX RDF
1	O. Sarbishei, Bijan Alizadeh, Masahiro Fujita	Arithmetic Circuits Verification without Looking for Internal Equivalences.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Subash Shankar, Masahiro Fujita	Rule-Based Approaches for Equivalence Checking of SpecC Programs.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Ken'ichiro Nagasaka, Atsushi Miyamoto, Masakuni Nagano, Hirokazu Shirado, Tetsuharu Fukushima, Masahiro Fujita	Motion control of a virtual humanoid that can perform real physical interactions with a human.	IROS	2008	DBLP DOI BibTeX RDF
1	Taro Takahashi, Toshimitsu Tsuboi, Takeo Kishida, Yasunori Kawanami, Satoru Shimizu, Masatsugu Iribe, Tetsuharu Fukushima, Masahiro Fujita	Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control.	ICRA	2008	DBLP DOI BibTeX RDF
1	Kenshu Seto, Masahiro Fujita	Custom Instruction Generation with High-Level Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Masahiro Fujita	Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.	DATE	2008	DBLP DOI BibTeX RDF
1	Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita	Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph.	J. UCS	2007	DBLP BibTeX RDF
1	Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita	Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction.	ATVA	2007	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Masahiro Fujita	Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.	ATVA	2007	DBLP DOI BibTeX RDF	Formal Verification, System on a Chip (SoC), Communication System, Canonical Representation, Sequential Equivalence Checking
1	Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satoshi Komatsu, Masahiro Fujita	Protocol Transducer Synthesis using Divide and Conquer approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	out-of-order transactions, large scale system on a chip, IP-based design, automatic protocol transducer synthesis, nonblocking transactions, design methodologies, communication protocols, protocol conversion, divide and conquer approach
1	Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita	Development and Verification of a Collaborative Printing Environment.	C5	2007	DBLP DOI BibTeX RDF
1	Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita	Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.	IESS	2007	DBLP DOI BibTeX RDF
1	David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan	Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	Formal verification, DSP, embedded software, VLIW
1	Yu Liu, Satoshi Komatsu, Masahiro Fujita	The AMS Extension to System Level Design Language - SpecC.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita	Synchronization Verification in System-Level Design with ILP Solvers.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Yu Liu, Satoshi Komatsu, Masahiro Fujita	Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita	Slicing-based Hardware/Software Co-design Methodology From Functional Specifications.	Electr. Notes Theor. Comput. Sci.	2006	DBLP DOI BibTeX RDF
1	Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita	Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs.	ISQED	2006	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Subash Shankar, S. Shunsuke	Equivalence checking: a rule-based approach.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra	Sequential Equivalence Checking.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Ken Matsui, Masahiro Fujita	Object-oriented analysis and specification for HW/SW co-design with UML diagrams.	ACST	2006	DBLP BibTeX RDF
1	Masahiro Fujita, Tasuku Nishihara, Daisuke Ando	System LSI distributed collaborative design environment for both designers and CAD developers/engineers.	C5	2006	DBLP DOI BibTeX RDF
1	Satoshi Komatsu, Masahiro Fujita	An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita	An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Satoshi Komatsu, Masahiro Fujita	Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	formal verification, High-level synthesis, equivalence checking, behavior synthesis
1	Gregory S. Hornby, Seiichi Takamura, Takashi Yamamoto, Masahiro Fujita	Autonomous evolution of dynamic gaits with two quadruped robots.	IEEE Transactions on Robotics	2005	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Shunsuke Sasaki, Ken Matsui	Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse.	IRI	2005	DBLP DOI BibTeX RDF
1	Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita	A modular architecture for humanoid robot navigation.	Humanoids	2005	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL.	MEMOCODE	2005	DBLP DOI BibTeX RDF
1	Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita	Synchronization verification in system-level design with ILP solvers.	MEMOCODE	2005	DBLP DOI BibTeX RDF
1	Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita	Real-Time Path Planning for Humanoid Robot Navigation.	IJCAI	2005	DBLP BibTeX RDF
1	Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita	System level design language extensions for timed/untimed digital-analog combined system design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	AMS extension, timed/untimed, synchronization, system level design, mixed-signal
1	Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita	Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.	FPT	2005	DBLP BibTeX RDF
1	Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita	A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot.	ICRA	2005	DBLP BibTeX RDF
1	Masahiro Fujita	Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.	CHARME	2005	DBLP DOI BibTeX RDF
1	Yu Liu, Satoshi Komatsu, Masahiro Fujita	AMS Extensions for Timed/Untimed System-Level Design Language.	FDL	2005	DBLP BibTeX RDF
1	Yosuke Bando, Takahiro Saito, Masahiro Fujita	Hexagonal storage scheme for interleaved frame buffers and textures.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
1	Tsutomu Sawada, Tsuyoshi Takagi, Yukiko Hoshino, Masahiro Fujita	Learning behavior selection through interaction based on emotionally grounded symbol concept.	Humanoids	2004	DBLP DOI BibTeX RDF
1	Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro Fujita	Associated Emotion and Its Expression in an Entertainment Robot QRIO.	ICEC	2004	DBLP DOI BibTeX RDF
1	Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Profio, Masahiro Fujita	Behavior Description and Control using Behavior Module for Personal Robot.	ICRA	2004	DBLP DOI BibTeX RDF
1	Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita	High Level Design Validation: Current Practices and Future Directions. (PDF / PS)	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Formal Verification of C Language Based VLSI Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Takashi Kanai	Precomputed Radiance Transfer with Spatially-Varying Lighting Effects.	CGIV	2004	DBLP DOI BibTeX RDF	PRT, global illumination, spherical harmonics, interactive graphics
1	Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa	An ethological and emotional basis for human-robot interaction.	Robotics and Autonomous Systems	2003	DBLP DOI BibTeX RDF
1	Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning, Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka	An Overview of RoboCup-2002 Fukuoka/Busan.	AI Magazine	2003	DBLP BibTeX RDF
1	Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada	Comparative Study On Verilog-Based And C-Based Hardware Design Education.	MSE	2003	DBLP DOI BibTeX RDF

Publications of "Masahiro Fujita" ( http://dblp.L3S.de/Authors/Masahiro_Fujita )