Search results for "Masahiro Numa"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa	Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	An Error Diagnosis Technique Based on Clustering of Elements.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa	Super-resolution technique for thermography with dual-camera system.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation.	JCP	2008	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa	Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Nobutaka Kuroki, Nobuhiro Oka, Masahiro Numa, Keisuke Yamamoto	An Evaluation of Triple Density Error Diffusion for Medical Monochrome LCDs.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	Leakage power reduction for clock gating scheme on PD-SOI.	ISCAS	2004	DBLP BibTeX RDF
1	Nobutaka Kuroki, Takahiro Manabe, Masahiro Numa	Adaptive arithmetic coding for image prediction errors.	ISCAS	2004	DBLP BibTeX RDF
1	Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata	A technique for high-speed circuits on SOI using look-ahead type active body bias control.	ISCAS	2004	DBLP BibTeX RDF
1	Hirokazu Masuda, Nobutaka Kuroki, Masahiro Numa, Kotaro Hirano	Layered blind deconvolution with interband prediction.	Systems and Computers in Japan	2000	DBLP DOI BibTeX RDF
1	Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita	A diagnosis method for single logic design errors in gate-level combinational circuits.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF

Publications of "Masahiro Numa" ( http://dblp.L3S.de/Authors/Masahiro_Numa )