| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama |
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.  |
IEICE Transactions  |
2012 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
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| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama |
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? |
Multiple-Valued Logic and Soft Computing |
2011 |
DBLP BibTeX RDF |
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| 1 | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. |
IEEE Trans. Circuits Syst. Video Techn. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama |
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama |
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama |
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama |
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Keita Tanji, Michitaka Kameyama |
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A low-power FPGA based on autonomous fine-grain power-gating. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Shota Ishihara, Michitaka Kameyama |
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama |
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation for Multi-Resolution Image Processing. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. |
ERSA |
2008 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama |
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. |
ERSA |
2008 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama |
FPGA implementation of a vehicle detection algorithm using three-dimensional information. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Sho Ogata, Michitaka Kameyama |
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama |
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi |
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama |
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama |
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama |
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama |
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama |
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama |
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama |
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
data-path design, scheduling, Automatic synthesis, module selection |
| 1 | Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama |
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama |
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama |
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. (PDF / PS) |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama |
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture |
| 1 | Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama |
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. |
ICRA |
2001 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama |
Architecture of a high-performance stereo vision VLSI processor. |
Advanced Robotics |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama |
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. |
ICRA |
1998 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama |
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. |
Systems and Computers in Japan |
1997 |
DBLP DOI BibTeX RDF |
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