Search results for "Masanori Hashimoto"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Shuta Kimura, Masanori Hashimoto, Takao Onoye	Body bias clustering for low test-cost post-silicon tuning.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Takaaki Okumura, Masanori Hashimoto	Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Stress Probability Computation for Estimating NBTI-Induced Delay Degradation.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Extracting Device-Parameter Variations with RO-Based Sensors.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.	FPL	2011	DBLP DOI BibTeX RDF
1	Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Yasumichi Takai, Masanori Hashimoto, Takao Onoye	Power gating implementation for noise mitigation with body-tied triple-well structure.	CICC	2011	DBLP DOI BibTeX RDF
1	Masanori Hashimoto	Run-time adaptive performance compensation using on-chip sensors.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Takehiko Amaki, Masanori Hashimoto, Takao Onoye	Jitter amplifier for oscillator-based true random number generator.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Kenichi Shinkai, Masanori Hashimoto	Device-parameter estimation with on-chip variation sensors considering random variability.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Takehiko Amaki, Masanori Hashimoto, Takao Onoye	An oscillator-based true random number generator with jitter amplifier.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto	Gate Delay Estimation in STA under Dynamic Power Supply Noise.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto	Impact of Self-Heating in Wire Interconnection on Timing.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Prediction of Self-Heating in Short Intra-Block Wires.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Shinyu Ninomiya, Masanori Hashimoto	Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Takashi Enami, Shinyu Ninomiya, Kenichi Shinkai, Shinya Abe, Masanori Hashimoto	Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue	Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration.	ISQED	2010	DBLP DOI BibTeX RDF
1	Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Clock skew reduction by self-compensating manufacturing variability with on-chip sensors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	on-chip sensors, self-compensation, clock distribution, manufacturing variability
1	Takaaki Okumura, Masanori Hashimoto	Setup time, hold time and clock-to-Q delay computation under dynamic supply noise.	CICC	2010	DBLP DOI BibTeX RDF
1	Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto	Gate delay estimation in STA under dynamic power supply noise.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling.	WISA	2010	DBLP DOI BibTeX RDF
1	Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato	Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto	An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto	Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Shingo Watanabe, Masanori Hashimoto, Toshinori Sato	A case for exploiting complex arithmetic circuits towards performance yield enhancement.	ISQED	2009	DBLP DOI BibTeX RDF
1	Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye	Coarse-grained dynamically reconfigurable architecture with flexible reliability.	FPL	2009	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	body bias clustering, performance compensation, layout, manufacturing variability, subthreshold circuits
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.	CICC	2009	DBLP DOI BibTeX RDF
1	Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng	High performance on-chip differential signaling using passive compensation for global communication.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Shinyu Ninomiya, Masanori Hashimoto	Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy.	SoCC	2009	DBLP DOI BibTeX RDF
1	Shinya Abe, Masanori Hashimoto, Takao Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa	Area-Efficient Reconfigurable Architecture for Media Processing.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera	Timing Analysis Considering Temporal Supply Voltage Fluctuation.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto	Impact of Well Edge Proximity Effect on Timing.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng	Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Shinya Abe, Masanori Hashimoto, Takao Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.	ISQED	2008	DBLP DOI BibTeX RDF	mesh-style clock distribution, clock skew, manufacturing variability
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout, body bias
1	Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto	Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise.	ISPD	2008	DBLP DOI BibTeX RDF	principal component analysis, gaussianization, power supply noise, statistical timing analysis
1	Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto	High performance current-mode differential logic.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye	Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Takashi Enami, Masanori Hashimoto, Takashi Sato	Decoupling capacitance allocation for timing with statistical noise model and timing analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng	On-chip high performance signaling using passive compensation.	ICCD	2008	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera	Timing Analysis Considering Spatial Power/Ground Level Variation.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto	Proposal of Metrics for SSTA Accuracy Evaluation.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa	Transistor Sizing of LCD Driver Circuit for Technology Migration.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye	Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Future Prediction of Self-Heating in Short Intra-Block Wires.	ISQED	2007	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa	A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto	Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto	On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto	Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Interconnect RL extraction at a single representative frequency.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye	A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.	ICCAD	2006	DBLP DOI BibTeX RDF	gate delay model, variability, static timing analysis, statistical timing analysis
1	Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye	Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.	ICCD	2006	DBLP BibTeX RDF
1	Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda	Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto	On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera	Successive Pad Assignment for Minimizing Supply Voltage Drop.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of On-Chip Inductance on Power Distribution Grid.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure.	ISQED	2005	DBLP DOI BibTeX RDF
1	Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa	Interconnect capacitance extraction for system LCD circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect capacitance, system LCD, capacitance extraction
1	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
1	Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera	Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera	Timing analysis considering temporal supply voltage fluctuation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto	On-chip thermal gradient analysis and temperature flattening for SoC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Return path selection for loop RL extraction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera	Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent waveform propagation for static timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera	Automatic Generation of Standard Cell Library in VDSM Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
1	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Representative frequency for interconnect R(f)L(f)C extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera	Timing analysis considering spatial power/ground level variation.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent Waveform Propagation for Static Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
1	Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera	Experimental Study on Cell-Base High-Performance Datapath Design.	IWLS	2002	DBLP BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera	Post-layout transistor sizing for power reduction in cell-based design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera	Crosstalk Noise Estimation for Generic RC Trees.	ICCD	2001	DBLP BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera	A performance optimization method by gate sizing using statistical static timing analysis.	ISPD	2000	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.	DAC	1999	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF

Publications of "Masanori Hashimoto" ( http://dblp.L3S.de/Authors/Masanori_Hashimoto )