| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Massimo Alioto |
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.  |
IEEE Trans. on Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey |
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger |
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabio Frustaci, Massimo Alioto, Pasquale Corsonello |
Tapered-Vth Approach for Energy-Efficient CMOS Buffers. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabio Frustaci, Pasquale Corsonello, Massimo Alioto |
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabio Frustaci, Pasquale Corsonello, Massimo Alioto |
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
DET FF topologies: A detailed investigation in the energy-delay-area domain. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Baccarin, David Esseni, Massimo Alioto |
A novel back-biasing low-leakage technique for FinFET forced stacks. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jerome Mitard, Liesbeth Witters, Thomas Y. Hoffmann |
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto |
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi |
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms. |
IEEE Trans. Dependable Sec. Comput. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Stéphane Badel, Yusuf Leblebici |
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy. |
Journal of Circuits, Systems, and Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi |
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi |
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti |
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Analysis of layout density in FinFET standard cells and impact of fin technology. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Paolo Bennati, Roberto Giorgi |
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer |
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto |
Design metrics for RTL level estimation of delay variability due to intradie (random) variations. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Analysis and Modeling of Energy Consumption in RLC Tree Circuits. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Armin Tajalli, Massimo Alioto, Yusuf Leblebici |
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Stéphane Badel, Yusuf Leblebici |
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Yusuf Leblebici |
Analysis and Design of Ultra-low Power Subthreshold MCML Gates. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Understanding Loading Effects of RC Uniform Interconnects. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti |
Leakage Power Analysis attacks: Theoretical analysis and impact of variations. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Analysis of the impact of random process variations in CMOS tapered buffers. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-Aware Design of Nanometer MCML Tapered Buffers. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici |
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi |
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-delay optimization in MCML tapered buffers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Gaetano Palumbo |
Explicit energy evaluation in RLC tree circuits with ramp inputs. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Luca Fondelli, Santina Rocchi |
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi |
A general model for differential power analysis attacks to static logic circuits. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer |
Improving the power-delay product in SCL circuits using source follower output stage. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
Mixed Full Adder topologies for high-performance low-power arithmetic circuits. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits. |
IEEE T. Instrumentation and Measurement |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Energy Consumption in RC Tree Circuits. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
A technique to design high entropy chaos-based true random bit generators. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Delay uncertainty due to supply variations in static and dynamic full adders. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
Analysis and design of MCML gates with hysteresis. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Nanometer MCML gates: models and design considerations. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design techniques for low-power cascaded CML gates. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
Long period pseudo random bit generators derived from a discretized chaotic map. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
An approach to the design of PFSCL gates. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Evaluation of energy consumption in RC ladder circuits driven by a ramp input. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
Positive-Feedback Source-Coupled Logic: a delay model. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
A gate-level strategy to design Carry Select Adders. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Massimo Alioto, Rosario Mita, Gaetano Palumbo |
Performance evaluation of the low-voltage CML D-latch topology. |
Integration |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design of MUX, XOR and D-latch SCL gates. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
An Approach to Energy Consumption Modeling in RC Ladder Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-delay trade-offs in SCL gates. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power estimation in adiabatic circuits: a simple and accurate model. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
CML ring oscillators: oscillation frequency. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Highly accurate and simple models for CML and ECL gates. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Novel Simple Models Of Cml Propagation Delay. (PDF / PS) |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
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