Search results for "Mateo Valero"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	Profiling and Optimizing Transactional Memory Applications.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Hardware transactional memory with software-defined conflicts.	TACO	2012	DBLP DOI BibTeX RDF
1	Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero	On the simulation of large-scale architectures using multiple application abstraction levels.	TACO	2012	DBLP DOI BibTeX RDF
1	Carlos Álvarez, Jesús Corbal, Mateo Valero	Dynamic Tolerance Region Computing for Multimedia.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	CPU Accounting for Multicore Processors.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero	Understanding the future of energy-performance trade-off via DVFS in HPC environments.	J. Parallel Distrib. Comput.	2012	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache.	Integration	2012	DBLP DOI BibTeX RDF
1	Bojan Maric, Jaume Abella, Mateo Valero	ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Optimal task assignment in multithreaded processors: a statistical approach.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero	TagTM - accelerating STMs with hardware tags for fast meta-data access.	DATE	2012	DBLP BibTeX RDF
1	Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman S. Unsal, Adrián Cristal, Mateo Valero	Hybrid Transactional Memory with Pessimistic Concurrency Control.	International Journal of Parallel Programming	2011	DBLP DOI BibTeX RDF
1	Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Scalable multicore architectures for long DNA sequence comparison.	Concurrency and Computation: Practice and Experience	2011	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero	A Highly Scalable Parallel Implementation of H.264.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Dynamic Cache Partitioning Based on the MLP of Cache Misses.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Juan Gonzalez, Judit Gimenez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero	Simulating Whole Supercomputer Applications.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, Mateo Valero	Assessing Accelerator-Based HPC Reverse Time Migration.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	Reverse time migration, Cell/B.E., geophysics, FPGA, GPU, accelerators
1	Jack Dongarra, Peter H. Beckman, Terry Moore, Patrick Aerts, Giovanni Aloisio, Jean-Claude Andre, David Barkai, Jean-Yves Berthou, Taisuke Boku, Bertrand Braunschweig, Franck Cappello, Barbara M. Chapman, Xuebin Chi, Alok N. Choudhary, Sudip S. Dosanjh, Thom H. Dunning, Sandro Fiore, Al Geist, Bill Gropp, Robert J. Harrison, Mark Hereld, Michael A. Heroux, Adolfy Hoisie, Koh Hotta, Zhong Jin, Yutaka Ishikawa, Fred Johnson, Sanjay Kale, Richard Kenway, David E. Keyes, Bill Kramer, Jesús Labarta, Alain Lichnewsky, Thomas Lippert, Bob Lucas, Barney Maccabe, Satoshi Matsuoka, Paul Messina, Peter Michielse, Bernd Mohr, Matthias S. Müller, Wolfgang E. Nagel, Hiroshi Nakashima, Michael E. Papka, Daniel A. Reed, Mitsuhisa Sato, Edward Seidel, John Shalf, David Skinner, Marc Snir, Thomas L. Sterling, Rick Stevens, Fred Streitz, Bob Sugar, Shinji Sumimoto, William Tang, John Taylor, Rajeev Thakur, Anne E. Trefethen, Mateo Valero, Aad van der Steen, Jeffrey S. Vetter, Peg Williams, Robert W. Wisniewski, Katherine A. Yelick	The International Exascale Software Project roadmap.	IJHPCA	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1	Augusto Vega, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Breaking the bandwidth wall in chip multiprocessors.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Vladimir Subotic, Roger Ferrer, José Carlos Sancho, Jesús Labarta, Mateo Valero	Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications.	Euro-Par	2011	DBLP DOI BibTeX RDF
1	Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero	Trace-driven simulation of multithreaded applications.	ISPASS	2011	DBLP DOI BibTeX RDF
1	Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.	PACT	2011	DBLP DOI BibTeX RDF
1	Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero	Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.	PACT	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.	PACT	2011	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache for optimistic concurrency.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Francisco J. Cazorla, Mateo Valero	A Quantitative Analysis of OS Noise.	IPDPS	2011	DBLP DOI BibTeX RDF
1	Ruken Zilan, Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero	An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.	MASCOTS	2011	DBLP DOI BibTeX RDF	Fine grain modeling, a methodology to build simulators, a simulation tool for multiï¿½??levels of shared resource architecture modeling, UltraSPARC T2, queueing modeling
1	Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero	Hybrid high-performance low-power and ultra-low energy reliable caches.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero	TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero	The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap.	PDP	2011	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero	From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.	ARC	2011	DBLP DOI BibTeX RDF
1	Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides	RVC-based time-predictable faulty caches for safety-critical systems.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	RMS-TM: a comprehensive benchmark suite for transactional memory systems.	ICPE	2011	DBLP DOI BibTeX RDF
1	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero	IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2011	DBLP DOI BibTeX RDF
1	Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero	RVC: a mechanism for time-analyzable real-time processors with faulty caches.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Mateo Valero	FIMSIM: A fault injection infrastructure for microarchitectural simulators.	ICCD	2011	DBLP DOI BibTeX RDF
1	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero	Utilization driven power-aware parallel job scheduling.	Computer Science - R&D	2010	DBLP DOI BibTeX RDF
1	Mateo Valero, Nacho Navarro	Multicore: The View from Europe.	IEEE Micro	2010	DBLP DOI BibTeX RDF	European research, HiPEAC, multicore
1	Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero	On the Problem of Evaluating the Performance of Multiprogrammed Workloads.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF
1	Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Long DNA Sequence Comparison on Multicore Architectures.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Vladimir Subotic, Jesús Labarta, Mateo Valero	Simulation environment for studying overlap of communication and computation.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero	Exploiting Inactive Rename Slots for Detecting Soft Errors.	ARCS	2010	DBLP DOI BibTeX RDF
1	Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	Discovering and understanding performance bottlenecks in transactional applications.	PACT	2010	DBLP DOI BibTeX RDF
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero	Efficient runahead threads.	PACT	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose	Power and thermal characterization of POWER6 system.	PACT	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Trends and techniques for energy efficient architectures.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero	Adapting cache partitioning algorithms to pseudo-LRU replacement policies.	IPDPS	2010	DBLP DOI BibTeX RDF
1	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero	BSLD threshold driven power management policy for HPC centers.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Task Superscalar: An Out-of-Order Task Pipeline.	MICRO	2010	DBLP DOI BibTeX RDF
1	Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero	Architectural Support for Fair Reader-Writer Locking.	MICRO	2010	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero	Load balancing using dynamic cache allocation.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmp architectures, load balancing, cache partitioning
1	Roberto Gioiosa, Sally A. McKee, Mateo Valero	Designing OS for HPC Applications: Scheduling.	CLUSTER	2010	DBLP DOI BibTeX RDF	Scheduling, Performance, Multiprocessor Systems, Operating system kernels, Super computers
1	Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero	A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications.	CLUSTER	2010	DBLP DOI BibTeX RDF	MPI, Communication-Computation Overlap
1	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero	Optimizing job performance under a given power constraint in HPC centers.	Green Computing Conference	2010	DBLP DOI BibTeX RDF
1	Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero	Overlapping communication and computation by using a hybrid MPI/SMPSs approach.	ICS	2010	DBLP DOI BibTeX RDF	hybrid MPI/SMPSs, MPI, parallel programming model, LINPACK
1	Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero	Scalability Analysis of Progressive Alignment on a Multicore.	CISIS	2010	DBLP DOI BibTeX RDF	clustalw, bioinformatics, multicore, multiple sequence alignment, cell
1	Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrián Cristal, Mateo Valero	Debugging programs that use atomic blocks and transactional memory.	PPOPP	2010	DBLP DOI BibTeX RDF	debugging, transactional memory
1	Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Thread to strand binding of parallel network applications in massive multi-threaded systems.	PPOPP	2010	DBLP DOI BibTeX RDF	ultrasparc t2, simultaneous multithreading, process scheduling, cmt
1	Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero	Effective communication and computation overlap with hybrid MPI/SMPSs.	PPOPP	2010	DBLP DOI BibTeX RDF	hybrid mpi/smpss, mpi, parallel programming model, linpack
1	Alejandro Rico, Alex Ramírez, Mateo Valero	Available task-level parallelism on the Cell BE.	Scientific Programming	2009	DBLP DOI BibTeX RDF
1	Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck	Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.	RASI	2009	DBLP BibTeX RDF
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	CPU Accounting in CMP Processors.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	DIA: A Complexity-Effective Decoding Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero	An Analyzable Memory Controller for Hard Real-Time CMPs.	Embedded Systems Letters	2009	DBLP DOI BibTeX RDF
1	Jesús Labarta, Eduard Ayguadé, Mateo Valero	BSC Vision Towards Exascale.	IJHPCA	2009	DBLP DOI BibTeX RDF
1	Jack Dongarra, Peter H. Beckman, Patrick Aerts, Franck Cappello, Thomas Lippert, Satoshi Matsuoka, Paul Messina, Terry Moore, Rick Stevens, Anne E. Trefethen, Mateo Valero	The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community.	IJHPCA	2009	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero	FlexDCP: a QoS framework for CMP architectures.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero	Hardware support for WCET analysis of hard real-time multicore systems.	ISCA	2009	DBLP DOI BibTeX RDF	wcet, interconnection network, multicore, hard real-time, real-time embedded systems, cache partitioning, analyzability
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.	PACT	2009	DBLP DOI BibTeX RDF
1	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum	Power-aware load balancing of large scale MPI applications.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Tim Harris, Adrián Cristal, Osman S. Unsal, Mateo Valero	Taking the heat off transactions: Dynamic selection of pessimistic concurrency control.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero	Clock gate on abort: Towards energy-efficient hardware Transactional Memory.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
1	Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero	EazyHTM: eager-lazy hardware transactional memory.	MICRO	2009	DBLP DOI BibTeX RDF	EazyHTM, transactional memory
1	M. Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero	Scalability of Macroblock-level Parallelism for H.264 Decoding.	ICPADS	2009	DBLP DOI BibTeX RDF
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Code Semantic-Aware Runahead Threads.	ICPP	2009	DBLP DOI BibTeX RDF
1	Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero	Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory.	HPCC	2009	DBLP DOI BibTeX RDF
1	Friman Sánchez, Alex Ramírez, Mateo Valero	Quantitative analysis of sequence alignment applications on multiprocessor architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	bioinformatics applications, parallel architectures, multiprocessor architectures, sequence comparison
1	Germán Rodríguez, Cyriel Minkenberg, Ramón Beivide, Ronald P. Luijten, Jesús Labarta, Mateo Valero	Oblivious routing schemes in extended generalized Fat Tree networks.	CLUSTER	2009	DBLP DOI BibTeX RDF
1	Mateo Valero	A european perspective on supercomputing.	ICS	2009	DBLP DOI BibTeX RDF	exaflop, exascale computing, supercomputing grids, supercomputing infrastructure, programming models, multicore architectures
1	Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero	QuakeTM: parallelizing a complex sequential application using transactional memory.	ICS	2009	DBLP DOI BibTeX RDF	game server, transactional memory
1	Germán Rodríguez, Ramón Beivide, Cyriel Minkenberg, Jesús Labarta, Mateo Valero	Exploring pattern-aware routing in generalized fat tree networks.	ICS	2009	DBLP DOI BibTeX RDF	k-ary n-trees, communication/traffic patterns, extended generalized fat trees (xgft's), network topologies, routing algorithms, clos networks
1	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Thread to Core Assignment in SMT On-Chip Multiprocessors.	SBAC-PAD	2009	DBLP DOI BibTeX RDF
1	Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero	Atomic quake: using transactional memory in an interactive multiplayer game server.	PPOPP	2009	DBLP DOI BibTeX RDF	benchmark, transactional memory, workload, quake
1	Chinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.	PPOPP	2009	DBLP DOI BibTeX RDF	parallel programming, concurrency, transactional memory, deadlocks, deadlock-detection
1	Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Nebelung: Execution Environment for Transactional OpenMP.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Compiler, OpenMP, Software Transactional Memory, Runtime system
1	Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith	Multicore Resource Management.	IEEE Micro	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	Power-efficient VLIW design using clustering and widening.	IJES	2008	DBLP DOI BibTeX RDF
1	Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero	Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero	Software-Controlled Priority Characterization of POWER5 Processor.	ISCA	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero	A Two-Level Load/Store Queue Based on Execution Locality.	ISCA	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero	A dynamic scheduler for balancing HPC applications.	SC	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero	Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.	ARCS	2008	DBLP DOI BibTeX RDF
1	Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luís Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee	Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.	EvoWorkshops	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero	Balancing HPC applications through smart allocation of resources in MT processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero	A distributed processor state management architecture for large-window processors.	MICRO	2008	DBLP DOI BibTeX RDF
1	Pedro A. Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Sally A. McKee	Evolutionary system for prediction and optimization of hardware architecture performance.	IEEE Congress on Evolutionary Computation	2008	DBLP DOI BibTeX RDF
1	Javier Verdú, Mario Nemirovsky, Mateo Valero	MultiLayer processing - an execution model for parallel stateful packet processing.	ANCS	2008	DBLP DOI BibTeX RDF	massively multithreaded architectures, multilayer processing, stateful, deep packet inspection, Snort
1	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.	ICPP	2008	DBLP DOI BibTeX RDF

Publications of "Mateo Valero" ( http://dblp.L3S.de/Authors/Mateo_Valero )