Search results for "Matteo Sonza Reorda"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michelangelo Grosso, Wilson Javier Perez Holguin, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, J. Velasco Medina	Software-Based Testing for System Peripherals.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	A new SBST algorithm for testing the register file of VLIW processors.	DATE	2012	DBLP BibTeX RDF
1	Luca Sterpone, Davide Sabena, Matteo Sonza Reorda	A New Fault Injection Approach for Testing Network-on-Chips.	PDP	2012	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Wilson Javier Perez Holguin, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina	Functional Verification of DMA Controllers.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Luciano Bonaria, Roberto Losco, Luciano Marcigot, Maurizio Straiotto	A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Matteo Sonza Reorda	A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda	On the functional test of Branch Prediction Units based on Branch History Table.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini	A Low-Cost Emulation System for Fast Co-verification and Debug.	European Test Symposium	2011	DBLP DOI BibTeX RDF	FPGA, debug, System-on-Chip, co-verification
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	At-speed delay fault testing, Power-aware Testing, Functional power
1	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
1	Jorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati	An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems.	DFT	2011	DBLP DOI BibTeX RDF
1	Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda	Fault injection analysis of transient faults in clustered VLIW processors.	DDECS	2011	DBLP DOI BibTeX RDF
1	Mauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi	Optimized embedded memory diagnosis.	DDECS	2011	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda	An effective methodology for on-line testing of embedded microprocessors.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani Poehls, Michelangelo Grosso, Matteo Sonza Reorda	A Hybrid Approach for Detection and Correction of Transient Faults in SoCs.	IEEE Trans. Dependable Sec. Comput.	2010	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, Matteo Sonza Reorda	Microprocessor Software-Based Self-Testing.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Maurizio Straiotto, Luciano Bonaria	A tester architecture suitable for MEMS calibration and testing.	ITC	2010	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Y. Zhang	A programmable BIST for DRAM testing and diagnosis.	ITC	2010	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An Exact and Efficient Critical Path Tracing Algorithm.	DELTA	2010	DBLP DOI BibTeX RDF	Fault models, Fault Simulation, Critical Path Tracing
1	Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda	Generating power-hungry test programs for power-aware validation of pipelined processors.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Wilson J. H. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, J. Velasco Medina	A software-based self-test methodology for system peripherals.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	An adaptive tester architecture for volume diagnosis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	M. Di Marzio, Michelangelo Grosso, Matteo Sonza Reorda, Luca Sterpone, G. Audisio, Marco Sabatini	A novel scalable and reconfigurable emulation platform for embedded systems verification.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda	An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization.	MTV	2010	DBLP DOI BibTeX RDF
1	Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone	Cumulative embedded memory failure bitmap display & analysis.	DDECS	2010	DBLP DOI BibTeX RDF
1	Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda	A hardware accelerated framework for the generation of design validation programs for SMT processors.	DDECS	2010	DBLP DOI BibTeX RDF
1	Paolo Rech, Michelangelo Grosso, Fabio Melchiori, D. Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda	Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena	An on-line fault detection technique based on embedded debug features.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda	Test Program Generation for Communication Peripherals in Processor-Based SoC Devices.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Design validation of multithreaded architectures using concurrent threads evolution.	SBCCI	2009	DBLP DOI BibTeX RDF	simulation based techniques, functional validation
1	Wilson J. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda	On the Generation of Functional Test Programs for the Cache Replacement Logic.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda	Automatic Functional Stress Pattern Generation for SoC Reliability Characterization.	European Test Symposium	2009	DBLP DOI BibTeX RDF	SoC reliability characterization
1	Davide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda	DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study.	VTS	2009	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis	A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.	DATE	2009	DBLP BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis	An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.	DFT	2009	DBLP DOI BibTeX RDF
1	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Matteo Sonza Reorda	Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Davide Appello	Evaluating Alpha-induced soft errors in embedded microprocessors.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante	Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Instruction hardening, SET, SEU, Infrastructure IP
1	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
1	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
1	Paolo Bernardi, Matteo Sonza Reorda	An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers.	DATE	2008	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.	MTV	2008	DBLP DOI BibTeX RDF
1	Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs.	DDECS	2008	DBLP DOI BibTeX RDF
1	Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs	CoRR	2007	DBLP BibTeX RDF
1	Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study	CoRR	2007	DBLP BibTeX RDF
1	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A System-layer Infrastructure for SoC Diagnosis.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP
1	Leticia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda	An optimized hybrid approach to provide fault detection and correction in SoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	fault correction, SoCs, fault detection, hybrid approach
1	Leticia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda	A software-based methodology for the generation of peripheral test sets based on high-level descriptions.	SBCCI	2007	DBLP DOI BibTeX RDF	RT-level test metrics, code coverage metrics, gate-level test metrics, test block, fault coverage, SoC testing
1	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault-emulation, software-based testing, FPGA, path-delay
1	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.	DATE	2007	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Safety Evaluation of NanoFabrics.	DFT	2007	DBLP DOI BibTeX RDF
1	Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.	DFT	2007	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante	Optimization of Self Checking FIR filters by means of Fault Injection Analysis.	DFT	2007	DBLP DOI BibTeX RDF
1	W. Di Palma, Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Automotive Microcontroller End-of-Line Test via Software-Based Methodologies.	MTV	2007	DBLP DOI BibTeX RDF
1	Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.	MTV	2007	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda	Extended Fault Detection Techniques for Systems-on-Chip.	DDECS	2007	DBLP BibTeX RDF
1	Leticia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda	A Hybrid Approach to Fault Detection and Correction in SoCs.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante	Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Efficient Techniques for Automatic Verification-Oriented Test Set Optimization.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	test-set optimization, evolutionary algorithm, Validation, microprocessor
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante	A New Hybrid Fault Detection Technique for Systems-on-a-Chip.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	SoC dependability, transient fault detection, infrastructure IP
1	Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante	Early, Accurate Dependability Analysis of CAN-Based Networked Systems.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	fault tolerance, fault injection, real-time and embedded systems, network architecture and design
1	Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	System-in-Package Testing: Problems and Solutions.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	IEEE1500 SECT, KGD, System-on-Chip, SoC, test access mechanism, SiP, System-in-Package, System-on-Package
1	Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Embedded Memory Diagnosis: An Industrial Workflow.	ITC	2006	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena	Fault Injection-based Reliability Evaluation of SoPCs.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries.	VTS	2006	DBLP DOI BibTeX RDF
1	Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	On the Automation of the Test Flow of Complex SoCs.	VTS	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.	DATE	2006	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante	Online hardening of programs against SEUs and SETs.	DFT	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda	Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.	MTV	2006	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek (eds.)	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006	DDECS	2006	DBLP BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante	Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante	New evolutionary techniques for test-program generation for complex microprocessor cores.	GECCO	2005	DBLP DOI BibTeX RDF	evolutionary algorithms, automatic test program generation
1	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
1	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Automatic Completion and Refinement of Verification Sets for Microprocessor Cores.	EvoWorkshops	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante	On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.	DSN	2005	DBLP DOI BibTeX RDF
1	Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
1	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.	DFT	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.	DFT	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.	MTV	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
1	Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda	Integrating BIST Techniques for On-Line SoC Testing.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	Evolutionary Simulation-Based Validation.	International Journal on Artificial Intelligence Tools	2004	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante	Efficient analysis of single event transients.	Journal of Systems Architecture	2004	DBLP DOI BibTeX RDF
1	Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
1	Matteo Sonza Reorda, Massimo Violante	A New Approach to the Analysis of Single Event Transients in VLSI Circuits.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	hardware emulation, fault injection, single event transient
1	Cecilia Metra, Matteo Sonza Reorda	Guest Editorial.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF
1	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Approach to Software-Implemented Fault Tolerance.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	fault injection, single event upsets, software-implemented fault tolerance
1	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	IEEE P1500, diagnosis, Hough transform, embedded memories
1	Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Program Generation: A Case Study.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Fulvio Corno, Matteo Sonza Reorda, S. Tosato, F. Esposito	Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems.	ITC	2004	DBLP DOI BibTeX RDF

Publications of "Matteo Sonza Reorda" ( http://dblp.L3S.de/Authors/Matteo_Sonza_Reorda )