Search results for "Memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos	Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory.	HPDC	2006	DBLP DOI BibTeX RDF	memory server, memory adaptation, local disk memory, remote memory capability, shared computational resource, network memory, memory malleability, MPI communication, cache memory, scientific application, virtual memory system
9	John G. Cleary, Murray Pearson, Husam Kinawi	The architecture of an optimistic CPU: the WarpEngine.	HICSS	1995	DBLP DOI BibTeX RDF	optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
8	Betty Prince	Embedded non-volatile memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM
8	Sajal K. Das, Sanjoy K. Sen	Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time
8	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
8	Peter S. Magnusson, Bengt Werner	Efficient memory simulation in SimICS.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	efficient memory simulation, SimICS, instruction level simulator, complex memory hierarchies, user level code, system level code, software caching mechanism, Simulator Translation Cache, STC, interpreted memory operations, complex memory simulation code, lazy storage allocation, well defined internal interface, generic memory simulation, user extensions, threaded code, runtime selection, statistics gathering, memory profiling, data structures, data structures, virtual machines, multiprocessors, storage management, storage allocation
8	Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde	Reflective-memory multiprocessor.	HICSS	1995	DBLP DOI BibTeX RDF	reflective-memory multiprocessor, hardware-supported data replication, multiple computers, memory semantics, reflective memory implementation, Encore Infinity, spinlocks, cache coherency problems, massive replication, recovery procedure, crashed nodes, reliability, fault tolerant computing, shared memory systems, distributed memory systems, system recovery, cache storage, cached architectures, distributed shared memory multiprocessor
8	Wei Zhao, Christos A. Papachristou	Architectural partitioning of control memory for application specific programmable processors.	ICCAD	1995	DBLP DOI BibTeX RDF	application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module
7	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
7	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
7	Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins	Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	dynamic data types, multimedia, low power, memory management, memory hierarchy, memory bandwidth, dynamic memory management, system-level exploration, memory footprint
7	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
7	Chen Ding, Chengliang Zhang, Xipeng Shen, Mitsunori Ogihara	Gated memory control for memory monitoring, leak detection and garbage collection.	Memory System Performance	2005	DBLP DOI BibTeX RDF	memory usage monitoring, object life, preventive memory management, memory leak, program phase
7	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
7	Leonidas I. Kontothanassis, Michael L. Scott	Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory.	HPCA	1996	DBLP DOI BibTeX RDF	memory-mapped network interfaces, cache fills, fine-grain access faults, parallel algorithms, protocols, message passing, latency, bandwidth, shared memory systems, distributed shared memory, distributed memory systems, network interfaces, network interfaces, memory-mapped
7	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
7	Milan Jovanovic, Milo Tomasevic, Veljko M. Milutinovic	A simulation-based comparison of two reflective memory approaches.	HICSS	1995	DBLP DOI BibTeX RDF	simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data
7	Ian Watson, Alasdair Rawsthorne	Decoupled pre-fetching for distributed shared memory.	HICSS	1995	DBLP DOI BibTeX RDF	partial evaluation (compilers), distributed shared memory environment, decoupled pre-fetching, global view, remote memory copies, user annotations, compile-time analysis, run-time prediction, irregular access patterns, dual processor structure, partial program evaluation, data fetches, parallel architectures, parallel machine, shared memory systems, distributed memory systems, memory architecture
7	Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic	A survey of distributed shared memory systems.	HICSS	1995	DBLP DOI BibTeX RDF	shared memory programming paradigm, physically distributed memories, classification taxonomy, classification criteria, DSM mechanism, hybrid DSM implementations, distributed systems, parallel programming, shared memory multiprocessors, shared memory systems, distributed memory systems, distributed shared memory systems, DSM systems
7	Dae Wook Bang, Yoo Kun Cho	Distributed shared memory for function-grained graph reduction machine.	PDP	1995	DBLP DOI BibTeX RDF	function-grained graph reduction machine, efficient DSM system, virtual global memory, function grained graph reduction machine, graph nodes, function applications, global memory access system, distributed graph nodes, H-object, memory coherence problem, weak coherence semantics, read operations, transputer network system, graph theory, resource allocation, parallel machines, parallel machine, distributed shared memory, distributed memory systems, processing elements, virtual storage, transputer systems
7	Masato Oguchi, Hitoshi Aida, Tadao Saito	A Proposal for a DSM Architecture Suitable for a Widely Distributed Environment and its Evaluation. (PDF / PS)	HPDC	1995	DBLP DOI BibTeX RDF	distributed shared memory architecture, widely distributed environment, functionally distributed computing, software programming, replicated shared memory, internal machine memory, SPARCstations, SCRAMNet, latency hiding techniques, performance evaluation, parallel architectures, shared memory systems, distributed memory systems, data prefetching, multi-thread programming, shared virtual memory
7	Sanjeev Setia, Mark S. Squillante, Satish K. Tripathi	Analysis of Processor Allocation in Multiprogrammed, Distributed-Memory Parallel Processing Systems.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	queueingtheory, independent jobs, multiple sequential tasks, job response time, distributed fork-joinqueueing system, processor allocation policy, bulk arrival queues, communicationoverhead, fork-join queues, modeling and analysis, scheduling, scheduling, parallel processing, parallel architectures, operating systems, shared-memory, synchronisation, shared memory systems, distributed memory systems, multiprogrammed, multiprogramming, processor allocation, distributed-memory, distributed memory, parallel processing systems, synchronization delay
6	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
6	Mojtaba Mehrara, Todd M. Austin	Reliability-aware data placement for partial memory protection in embedded processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	memory lifetime, partial memory protection, selective data placement, embedded systems, soft errors
6	Yi Feng, Emery D. Berger	A locality-improving dynamic memory allocator.	Memory System Performance	2005	DBLP DOI BibTeX RDF	vam, memory management, virtual memory, paging, fragmentation, allocator, cache locality
6	Mark S. Ackerman, Christine Halverson	Organizational Memory as Objects, Processes, and Trajectories: An Examination of Organizational Memory in Use.	Computer Supported Cooperative Work	2004	DBLP DOI BibTeX RDF	memory reuse, trajectories of information, knowledge management, distributed cognition, organizational memory, contextualization, boundary objects, corporate memory, information reuse, collective memory
6	Chitra Natarajan, Bruce Christenson, Faye A. Briggs	A study of performance impact of memory controller features in multi-processor server environment.	WMPI	2004	DBLP DOI BibTeX RDF	memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact
6	Mark S. Ackerman, David W. McDonald	Collaborative Support for Informal Information in Collective Memory Systems.	Information Systems Frontiers	2000	DBLP DOI BibTeX RDF	community memory, informal information, information refining, collaborative help, information retrieval, computer-supported cooperative work, CSCW, information systems, CMC, computer-mediated communications, information access, organizational memory, help, group memory, corporate memory, incremental formalization
6	Zaid Al-Ars, A. J. van de Goor	Impact of memory cell array bridges on the faulty behavior in embedded DRAMs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	memory cell array bridges, memory fault models, dynamic faulty behavior, dynamic RAM, fault simulation, memory tests, circuit simulation, random-access storage, integrated memory circuits, functional faults, embedded DRAMs, fault primitives, faulty behavior
6	Chi-Min Lin, Tien-Fu Chen	Dynamic memory management for real-time embedded Java chips.	RTCSA	2000	DBLP DOI BibTeX RDF	storage management chips, dynamic runtime memory management, real-time embedded Java chips, CPU design, hardware-assisted scheme, dynamic garbage collection mechanism, predictable memory allocation time, data transition events, circular heap, simulation, Java, embedded systems, response time, memory architecture, memory architecture, storage allocation, coprocessors, resource constraints, real-time constraints, co-processor
6	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
6	Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Memory System Support for Image Processing.	IEEE PACT	1999	DBLP DOI BibTeX RDF	bus utilization, image processing, virtual memory, memory architecture, memory bandwidth, memory latency, cache efficiency
6	Mark S. Ackerman	Augmenting Organizational Memory: A Field Study of Answer Garden.	ACM Trans. Inf. Syst.	1998	DBLP DOI BibTeX RDF	community memory, CSCW, computer-supported cooperative work, field studies, organizational memory, group memory, collective memory
6	Andreas Moshovos, Gurindar S. Sohi	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.	MICRO	1997	DBLP BibTeX RDF	DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation
6	Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An	A Scalable Memory System Design.	VLSI Design	1997	DBLP DOI BibTeX RDF	scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed
6	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
6	V. Kim, T. Chen	Assessing SRAM test coverage for sub-micron CMOS technologies.	VTS	1997	DBLP DOI BibTeX RDF	submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
6	Mark G. Karpovsky, Vyacheslav N. Yarmolik	Transparent random access memory testing for pattern sensitive faults.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	transparent memory testing, pseudoexhaustive memory testing, built-in self-test, memory testing, signature analysis, random access memory, pattern sensitive faults
6	Michael Gerndt	"Programming Shared Virtual Memory Multiprocessor".	PDP	1996	DBLP DOI BibTeX RDF	shared virtual memory multiprocessors, compute intensive scientific applications, physical memory distribution, message passing programming model, task parallel programming model, shared virtual address space, parallel programming, parallel programming, operating system, message passing, parallel machines, parallel machines, shared memory systems, distributed memory systems, operating systems (computers), virtual storage
6	Wolfgang K. Giloi, Ulrich Brüning, Wolfgang Schröder-Preikschat	MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.	PDP	1996	DBLP DOI BibTeX RDF	maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors
6	Luís Moura Silva, João Gabriel Silva, Simon Chapple	Implementing Distributed Shared Memory on Top of MPI: The DSMPI Library.	PDP	1996	DBLP DOI BibTeX RDF	DSMPI library, parallel library, performance, scalability, parallel programming, parallel programming, MPI, message passing, message passing, consistency, shared memory systems, distributed shared memory, distributed memory systems, software performance evaluation, software libraries, software portability, software portability, distributed memory machines, coherence protocols, workstation network, programming interface, Cray T3D
6	A. M. del Corral, José M. Llabería	Access order to avoid inter-vector-conflicts in complex memory systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	access order, inter-vector-conflicts, complex memory systems, vector processor accessing vectors, concurrent memory access, inter-conflicts, performance evaluation, performance, vector processor systems, memory subsystem, memory modules
6	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
6	Santanu Dutta, Wayne Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
6	Gyungho Lee	An assessment of COMA multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
6	Syed Masud Mahmud, L. Tissa Samaratunga	Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	memory bandwidth analysis, hierarchicalmultiprocessors, model decomposition, steady-state flow analysis, memory cycle, hierarchical interconnection network, performance evaluation, multiprocessor interconnection networks, shared memory systems, memory architecture, failure analysis
6	David M. Koppelman	Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	memory traffic, difference coding, memory addresses, shared memory parallel computer, trace-drivensimulation, traffic volume, lower cost, lower latency network, networklatency, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, memories, shared memory systems, storage management, buffer storage, processing elements, coherent cache
6	Ravi Ganesan, Shlomo Weiss	Scalar Memory References in Pipelined Multiprocessors: A Performance Study.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	scalar memory references, pipelined multiprocessors, high memory bandwidth, memory cycle, processor cycle time, bank reservation time, bank busy time, performance evaluation, probability, Markov chain, Markov processes, parallel machines, Markov models, storage management, simulation results, pipeline processing, state space, transition probabilities, pipelined computers, memory bank
6	Mark A. Holliday, Carla Schlatter Ellis	Accuracy of Memory Reference Traces of Parallel Computations in Trace-Driven Simulation.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	load sequences, memory reference traces, trace-drive simulation, global trace, shared memory multiprocessingenvironment, address change points, address affecting points, process traces, intrinsic trace, address flow graph, store sequences, partial program reexecution, graph-traceable, parallel program, parallel programming, parallel computations, memory management, storage management, memory architecture, path expressions
5	Byunghyun Jang, Dana Schaa, Perhaad Mistry, David R. Kaeli	Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	General-purpose computation on GPUs (GPGPUs), memory access pattern, memory selection, memory coalescing, data-parallel architectures, vectorization, data parallelism, memory optimization, GPU computing
5	Lian Li 0002, Hui Feng, Jingling Xue	Compiler-directed scratchpad memory management via graph coloring.	TACO	2009	DBLP DOI BibTeX RDF	live range splitting, memory coloring, graph coloring, memory allocation, Scratchpad memory, register coalescing, software-managed cache
5	Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch	Disaggregated memory for expansion and sharing in blade servers.	ISCA	2009	DBLP DOI BibTeX RDF	disaggregated memory, memory blades, memory capacity expansion, power and cost efficiencies
5	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
5	Richard F. Freitas	Storage class memory: technology, systems and applications.	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	storage class memory, phase change memory, nonvolatile memory
5	Yong Cao, Wenjian Luo	Novel Associative Memory Retrieving Strategies for Evolutionary Algorithms in Dynamic Environments.	ISICA	2009	DBLP DOI BibTeX RDF	memory retrieving strategy, evolutionary algorithms, memory, associative memory, dynamic optimization problems
5	Yungbum Jung, Kwangkeun Yi	Practical memory leak detector based on parameterized procedural summaries.	ISMM	2008	DBLP DOI BibTeX RDF	program analysis, abstract interpretation, memory management, error detection, shape analysis, memory leaks
5	Ross McIlroy, Peter Dickman, Joe Sventek	Efficient dynamic heap allocation of scratch-pad memory.	ISMM	2008	DBLP DOI BibTeX RDF	on-core memory, concurrency, memory management
5	Stephen Curial, Peng Zhao, José Nelson Amaral, Yaoqing Gao, Shimin Cui, Raúl Silvera, Roch Archambault	MPADS: memory-pooling-assisted data splitting.	ISMM	2008	DBLP DOI BibTeX RDF	memory pooling, optimization, compilers, memory management, allocation strategies
5	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Combinable memory-block transactions.	SPAA	2008	DBLP DOI BibTeX RDF	memory-block transactions, priority write, read-modify-write, shared memory, transactional memory, queue, contention, combining, stack, linearizability, semaphore
5	Vaiva Kalnikaité, Steve Whittaker	Cueing digital memory: how and why do digital notes help us remember?	BCS HCI	2008	DBLP DOI BibTeX RDF	digital memory, handwritten notes, prosthetic memory, remembering, memory, notes
5	Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Benjamin G. Zorn	Archipelago: trading address space for reliability and security.	ASPLOS	2008	DBLP DOI BibTeX RDF	Archipelago, probabilistic memory safety, randomized algorithms, virtual memory, buffer overflow, dynamic memory allocation, memory errors
5	Jung-Hoon Lee	Next High Performance and Low Power Flash Memory Package Structure.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory
5	Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	auto vectorizing compiler, unaligned memory operations, SIMD extensions, video codec applications, unaligned memory accesses, H.264/AVC media codec, memory architecture, data level parallelism
5	Seok-Young Jang, Sang-Hwa Chung, Won-Ju Yoon, Seong-Joon Lee	An Effective Design of an Active RFID Reader Using a Cache of Tag Memory Data.	PAKDD Workshops	2007	DBLP DOI BibTeX RDF	Tag Memory Data, Logical Memory, Logical Cache Memory
5	Huu Hai Nguyen, Martin C. Rinard	Detecting and eliminating memory leaks using cyclic memory allocation.	ISMM	2007	DBLP DOI BibTeX RDF	cyclic memory allocation, failure-oblivious computing, memory leaks
5	Delvin C. Defoe, Rob LeGrand, Ron K. Cytron	On the connection between functional programming languages and real-time Java scoped memory.	JTRES	2007	DBLP DOI BibTeX RDF	scoped memory, real-time, performance analysis, data structures, programming languages, functional programming, memory, memory management, real-time Java
5	Andreas Lachenmann, Pedro José Marrón, Matthias Gauger, Daniel Minder, Olga Saukh, Kurt Rothermel	Removing the memory limitations of sensor networks with flash-based virtual memory.	EuroSys	2007	DBLP DOI BibTeX RDF	wireless sensor networks, flash memory, virtual memory, memory layout
5	Vaiva Kalnikaité, Steve Whittaker	Software or wetware?: discovering when and why people use digital prosthetic memory.	CHI	2007	DBLP DOI BibTeX RDF	digital memory, prosthetic memory, remembering, speech browsing, memory, speech retrieval, notes
5	Ke Ning, David R. Kaeli	External memory page remapping for embedded multimedia systems.	LCTES	2007	DBLP DOI BibTeX RDF	memory coloring, memory page remapping, embedded systems, memory controllers
5	Swapan Kumar Ray, Sabyasachi Dutta, Abhik Kumar Saha	A Low-Cost Pipelineed Multi-Lingual E-Dictionary Using a Pipelined CTAM.	ICCTA	2007	DBLP DOI BibTeX RDF	Address-To-Content Memory (ATCM), Content-To-Address Memory (CTAM), Pipelined CTAM (PCTAM), Low-Cost PCTAM, Content Addresseble Memory (CAM), Assosiative Memory (AM), Pipelined AM (PAM), Multi-Lingual E-Dictionary (MLeD), Pipelined MLeD (PMLeD), Universal Dictionary Server (UDS)
5	David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor	Systematic dynamic memory management design methodology for reduced memory footprint.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Multimedia embedded systems, custom dynamic memory management, reduced memory footprint, operating systems, memory management
5	Andrew M. Cheadle, A. J. Field, J. W. Ayres, Neil Dunn, Richard A. Hayden, Johan Nyström-Persson	Visualising dynamic memory allocators.	ISMM	2006	DBLP DOI BibTeX RDF	visualisation of objects, garbage collection, memory management, dynamic memory allocation, language implementation
5	Richard L. Hudson, Bratin Saha, Ali-Reza Adl-Tabatabai, Ben Hertzberg	McRT-Malloc: a scalable transactional memory allocator.	ISMM	2006	DBLP DOI BibTeX RDF	synchronization, memory management, transactional memory, runtimes
5	Scott Schneider, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Scalable locality-conscious multithreaded memory allocation.	ISMM	2006	DBLP DOI BibTeX RDF	synchronization-free, shared memory, multithreading, memory management, non-blocking
5	Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca	A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	memory bandwidth, memory wall, processing-in-memory
5	Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight	Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Active memory systems, address remapping, flexible memory controller architecture, distributed shared memory, cache coherence protocol
5	Jong Won Park	Multiaccess Memory System for Attached SIMD Computer.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	prime memory system, multiaccess memory system, conflict-free memory system, routing circuit, SIMD computer, address calculation
5	Robert C. Steinke, Gary J. Nutt	A unified theory of shared memory consistency.	J. ACM	2004	DBLP DOI BibTeX RDF	memory consistency model lattice, memory consistency models, Distributed shared memory systems
5	Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani	Instruction combining for coalescing memory accesses using global code motion.	Memory System Performance	2004	DBLP DOI BibTeX RDF	instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures
5	Michael W. Hicks, J. Gregory Morrisett, Dan Grossman, Trevor Jim	Experience with safe manual memory-management in cyclone.	ISMM	2004	DBLP DOI BibTeX RDF	unique pointers, memory management, regions, memory safety, cyclone
5	Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher	A low-power memory hierarchy for a fully programmable baseband processor.	WMPI	2004	DBLP DOI BibTeX RDF	baseband processor, multi-tasked processor, task interleaving, memory hierarchy, low-power memory
5	Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi	An empirical performance analysis of commodity memories in commodity servers.	Memory System Performance	2004	DBLP DOI BibTeX RDF	performance analysis, performance measurement, memory modules, memory system performance
5	Yan Solihin, Jaejin Lee, Josep Torrellas	Correlation Prefetching with a User-Level Memory Thread.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	correlation prefetching, memory-side prefetching, intelligent memory architecture, Prefetching, heterogeneous system, processing-in-memory, helper threads
5	Hyung Gyu Lee, Naehyuck Chang	Energy-aware memory allocation in heterogeneous non-volatile memory systems.	ISLPED	2003	DBLP DOI BibTeX RDF	memory allocation, non-volatile memory, low-power memory
5	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
5	Yan Solihin, Josep Torrellas, Jaejin Lee	Using a User-Level Memory Thread for Correlation Prefetching. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	intelligent memory, correlation prefetching, caches, computer architecture, memory hierarchies, threads, data prefetching, processing-in-memory
5	Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya	Automatic generation of embedded memory wrapper for multiprocessor SoC.	DAC	2002	DBLP DOI BibTeX RDF	dystem-on-chip, memory wrapper generation, embedded memory, memory access
5	Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli	Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design.	ISSS	2002	DBLP DOI BibTeX RDF	memory wrapper generation, system-on-chip, embedded memory, memory access
5	Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
5	Bülent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, T. Basil Smith	Hardware Compressed Main Memory: Operating System Support and Performance Evaluation.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Memory compression, memory and cache performance, webserver performance, memory management
5	Jeffrey Scott Vitter	External memory algorithms and data structures.	ACM Comput. Surv.	2001	DBLP DOI BibTeX RDF	multilevel memory, dynamic, sorting, block, B-tree, online, batched, I/O, out-of-core, disk, external memory, secondary storage, hierarchical memory, extendible hashing, multidimensional access methods
5	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis
5	Chen Ding, Ken Kennedy	The Memory Bandwidth Bottleneck and its Amelioration by a Compiler. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	memory performance model, array reduction, store elimination, memory hierarchy, compiler optimizations, Memory bandwidth, loop fusion
5	Gustavo Rodriguez-Rivera, Michael Spertus, Charles Fiterman	Conservative Garbage Collection for General Memory Allocators.	ISMM	2000	DBLP DOI BibTeX RDF	automatic memory management, memory allocation, conservative garbage collection
5	Miseon Choi, Hye-Sook Yoon, Eun-Mi Song, Young-Keol Kim, Young-Kuk Kim, Seong-il Jin, Mi-kyong Han, Wan Choi	Two-step backup mechanism for real-time main memory database recovery.	RTCSA	2000	DBLP DOI BibTeX RDF	back-up procedures, two-step backup mechanism, real-time main-memory database recovery, system recovery time, undo/redo logs, backup processing, shadow memory area, stable memory, backup buffer, backup disk, worst-case performance analysis, real-time systems, predictability, database management systems, checkpointing, transaction processing, transaction processing, response time, system recovery, buffer storage, logging, disk I/O
5	JaeWoong Chung, Byeong Hag Seong, Kyu Ho Park, Daeyeon Park	Moving Home-Based Lazy Release Consistency for Shared Virtual Memory Systems. (PDF / PS)	ICPP	1999	DBLP DOI BibTeX RDF	software DSM system, parallel processing, distributed computing, shared memory, memory consistency, Shared Virtual Memory, Release Consistency
5	Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias, Marco Zagha	Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1997	DBLP DOI BibTeX RDF	Memory bank contention, memory delays, parallel machine models, parallel algorithms, performance analysis, multiprocessors, shared memory
5	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
5	Myoung Kwon Tcheun, Hyunsoo Yoon, Seung Ryoul Maeng	An adaptive sequential prefetching scheme in shared-memory multiprocessors. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	adaptive sequential prefetching scheme, hardware controlled scheme, high sequentiality, shared-memory multiprocessors, shared memory systems, application programs, sequentiality, memory accesses
5	Anand Sivasubramaniam	Reducing the Communication Overhead of Dynamic Applications on Shared Memory Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	dynamic communication behavior, invalidation-based protocols, receiver-initiated communication, write overheads, redundant updates, intelligent sender-initiated data transfer mechanisms, competitive update mechanism, scalability, geographical information systems, shared memory multiprocessors, shared memory systems, data transfer, communication overhead, temporal locality, spatial locality, shared memory architectures, shared address space, performance benefits, dynamic applications