Search results for "Memory architecture exploration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Zhongbo Cao, Ramon Mercado, Diane T. Rover	System-level memory modeling for bus-based memory architecture exploration.	EIT	2009	DBLP DOI BibTeX RDF
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	Memory Architecture Exploration Framework for Cache Based Embedded SOC.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.	ACM Trans. Embedded Comput. Syst.	2012	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas	Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Memory architecture exploration, High level synthesis, Memory optimization, Multi-media, Code transformation
1	Rahul Jain, Preeti Ranjan Panda	Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor	Incremental hierarchical memory size estimation for steering of loop transformations.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Data optimization, memory architecture exploration, memory size estimation, high-level synthesis, code transformation
1	Mile K. Stojcev	Memory architecture exploration for programmable embedded systems; Peter Grun, Nikil Dutt, Alexandru Nicolau. Kluwer Academic Publishers, Boston. 2003. Hardcover, pp 128, plus XVII, ISBN 1-4020-7324-0.	Microelectronics Reliability	2004	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Storage requirement estimation for optimized design of data intensive applications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	data optimization, memory architecture exploration, high-level synthesis, code transformation, Size estimation
1	Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo	Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.	DATE	2004	DBLP DOI BibTeX RDF
1	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Memory architecture exploration for programmable embedded systems.		2003	RDF
1	Diederik Verkest, Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Kris Croes, Miguel Miranda, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man	Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.	VLSI Signal Processing	1999	DBLP DOI BibTeX RDF
1	Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man	Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
1	Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong	Fast and Extensive System-Level Memory Exploration for ATM Applications. (PDF / PS)	ISSS	1997	DBLP DOI BibTeX RDF	memory exploration, memory optimization, network applications