Search results for "Memory-Level Parallelism"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Stijn Eyerman, Lieven Eeckhout	Memory-level parallelism aware fetch policies for simultaneous multithreading processors.	TACO	2009	DBLP DOI BibTeX RDF	Fetch Policy, Simultaneous Multithreading (SMT), Memory-Level Parallelism (MLP)
3	Huiyang Zhou, Thomas M. Conte	Enhancing memory level parallelism via recovery-free value prediction.	ICS	2003	DBLP DOI BibTeX RDF	recovery-free value prediction, prefetching, memory disambiguation, memory level parallelism
2	Stijn Eyerman, Lieven Eeckhout	A Memory-Level Parallelism Aware Fetch Policy for SMT Processors.	HPCA	2007	DBLP DOI BibTeX RDF
2	James Tuck, Luis Ceze, Josep Torrellas	Scalable Cache Miss Handling for High Memory-Level Parallelism.	MICRO	2006	DBLP DOI BibTeX RDF
2	Michael Gschwind	Chip multiprocessing and the cell broadband engine.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
2	Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir	Overlapping dependent loads with addressless preload.	PACT	2006	DBLP DOI BibTeX RDF	instruction and issue window, pointer-chasing loads, data prefetching, memory-level parallelism
2	Huiyang Zhou, Thomas M. Conte	Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Single data stream architectures
2	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF
1	I-Jui Sung, Nasser Anssari, John A. Stratton, Wen-mei W. Hwu	Data Layout Transformation Exploiting Memory-Level Parallelism in Structured Grid Many-Core Applications.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	George Patsilaras, Niket K. Choudhary, James Tuck	Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era.	TACO	2012	DBLP DOI BibTeX RDF
1	Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John	MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.	PACT	2011	DBLP DOI BibTeX RDF
1	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
1	Karthik Ganesan, Jungho Jo, Lizy K. John	Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads.	ISPASS	2010	DBLP DOI BibTeX RDF
1	I-Jui Sung, John A. Stratton, Wen-mei W. Hwu	Data layout transformation exploiting memory-level parallelism in structured grid many-core applications.	PACT	2010	DBLP DOI BibTeX RDF
1	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Aérgia: exploiting packet latency slack in on-chip networks.	ISCA	2010	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
1	Dan Gibson, David A. Wood	Forwardflow: a scalable core for power-constrained CMPs.	ISCA	2010	DBLP DOI BibTeX RDF	scalable core, chip multiprocessor (cmp), power
1	Jiayuan Meng, David Tarjan, Kevin Skadron	Dynamic warp subdivision for integrated branch and memory divergence tolerance.	ISCA	2010	DBLP DOI BibTeX RDF	branch divergence, memory divergence, cache, warp, latency hiding, simd
1	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
1	Sunpyo Hong, Hyesoon Kim	An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness.	ISCA	2009	DBLP DOI BibTeX RDF	GPU architecture, warp level parallelism, analytical model, performance estimation, cuda, memory level parallelism
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Practical off-chip meta-data for temporal memory streaming.	HPCA	2009	DBLP DOI BibTeX RDF
1	Rangyu Deng, Weixia Xu, Qiang Dou, Hongwei Zhou, Zefu Dai, Haiyan Chen	An efficient stream memory architecture for heterogeneous multicore processor.	ISCC	2009	DBLP DOI BibTeX RDF
1	Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout	MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson	Latency-tolerant software pipelining in a production compiler.	CGO	2008	DBLP DOI BibTeX RDF	latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
1	Gordon B. Bell, Mikko H. Lipasti	Skewed redundancy.	PACT	2008	DBLP DOI BibTeX RDF	distributed processing, error tolerance, memory-level parallelism
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads to improve SMT performance.	HPCA	2008	DBLP DOI BibTeX RDF
1	Davy Genbrugge, Lieven Eeckhout	Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Simulation, Modeling techniques, Performance Analysis and Design Aids
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A Flexible Heterogeneous Multi-Core Architecture.	PACT	2007	DBLP DOI BibTeX RDF
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads: Reducing Resource Contention in SMT Processors.	PACT	2007	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	value prediction, memory-level parallelism, runahead execution, Single data stream architectures
1	Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt	A Case for MLP-Aware Cache Replacement.	ISCA	2006	DBLP DOI BibTeX RDF
1	Yuan Chou, Lawrence Spracklen, Santosh G. Abraham	Store Memory-Level Parallelism Optimizations for Commercial Applications.	MICRO	2005	DBLP DOI BibTeX RDF
1	Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood	Exploring Processor Design Options for Java-Based Middleware.	ICPP	2005	DBLP DOI BibTeX RDF	Java, Middleware, CMP, workloads, ILP, Characterization
1	Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi	Store-Ordered Streaming of Shared Memory.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Dongkeun Kim, Donald Yeung	A study of source-level compiler algorithms for automatic construction of pre-execution code.	ACM Trans. Comput. Syst.	2004	DBLP DOI BibTeX RDF	pre-execution, prefetch conversion, speculative loop parallelization, multithreading, program slicing, Data prefetching, memory-level parallelism