Search results for "Michael Bedford Taylor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson, Michael Bedford Taylor	GreenDroid: An architecture for the Dark Silicon Age.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Steven Swanson, Michael Bedford Taylor	Greendroid: Exploring the next evolution in smartphone application processors.	IEEE Communications Magazine	2011	DBLP DOI BibTeX RDF
1	Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Vikram Bhatt, Jonathan Babb, Steven Swanson, Michael Bedford Taylor	The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Saturnino Garcia, Donghwan Jeon, Christopher M. Louie, Michael Bedford Taylor	Kremlin: rethinking and rebooting gprof for the multicore age.	PLDI	2011	DBLP DOI BibTeX RDF
1	Jack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb, Vikram Bhatt, Steven Swanson, Michael Bedford Taylor	An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.	FPL	2011	DBLP DOI BibTeX RDF
1	Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson	QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.	MICRO	2011	DBLP DOI BibTeX RDF
1	Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson	Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.	FCCM	2011	DBLP DOI BibTeX RDF
1	Donghwan Jeon, Saturnino Garcia, Christopher M. Louie, Michael Bedford Taylor	Kismet: parallel speedup estimates for serial programs.	OOPSLA	2011	DBLP DOI BibTeX RDF
1	Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor	Efficient complex operators for irregular codes.	HPCA	2011	DBLP DOI BibTeX RDF
1	Donghwan Jeon, Saturnino Garcia, Christopher M. Louie, Sravanthi Kota Venkata, Michael Bedford Taylor	Kremlin: like gprof, but for parallelization.	PPOPP	2011	DBLP DOI BibTeX RDF
1	Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor	Conservation cores: reducing the energy of mature computations.	ASPLOS	2010	DBLP DOI BibTeX RDF	conservation core, heterogeneous many-core, utilization wall, patching
1	Yi Zhu, Yuanfang Hu, Michael Bedford Taylor, Chung-Kuan Cheng	Energy and switch area optimizations for FPGA global routing architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low power, global routing
1	Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon, Anshuman Gupta, Christopher M. Louie, Saturnino Garcia, Serge Belongie, Michael Bedford Taylor	SD-VBS: The San Diego Vision Benchmark Suite.	IISWC	2009	DBLP DOI BibTeX RDF
1	Yi Zhu, Michael Bedford Taylor, Scott B. Baden, Chung-Kuan Cheng	Advancing supercomputer performance through interconnection topology synthesis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung-Kuan Cheng	FPGA global routing architecture optimization using a multicommodity flow approach.	ICCD	2007	DBLP DOI BibTeX RDF
1	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
1	Michael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal	Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.	ISCA	2004	DBLP DOI BibTeX RDF
1	Jason Sungtae Kim, Michael Bedford Taylor, Jason E. Miller, David Wentzlaff	Energy characterization of a tiled architecture processor with on-chip networks.	ISLPED	2003	DBLP DOI BibTeX RDF	raw microprocessor, scalar operand network, power, tile
1	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.	HPCA	2003	DBLP DOI BibTeX RDF
1	Michael Bedford Taylor, Jason Sungtae Kim, Jason E. Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jae W. Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal	The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs.	IEEE Micro	2002	DBLP DOI BibTeX RDF
1	Elliot Waingold, Michael Bedford Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman P. Amarasinghe, Anant Agarwal	Baring It All to Software: Raw Machines.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Bedford Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal	The RAW benchmark suite: computation structures for general purpose computing.	FCCM	1997	DBLP DOI BibTeX RDF

Publications of "Michael Bedford Taylor" ( http://dblp.L3S.de/Authors/Michael_Bedford_Taylor )