Search results for "Michael Gschwind"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Valentina Salapura, Michael Gschwind, Jens Knoop	Guest Editorial: Parallel Systems and Compilers.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	Ruud A. Haring, Martin Ohmacht, Thomas Fox, Michael Gschwind, David L. Satterfield, Krishnan Sugavanam, Paul Coteus, Philip Heidelberger, Matthias A. Blumrich, Robert Wisniewski, Alan Gara, George L.-T. Chiu, Peter A. Boyle, Norman Chist, Changhoan Kim	The IBM Blue Gene/Q Compute Chip.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Michael Gschwind, Valentina Salapura, Catherine Trammell, Sally A. McKee	SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time.	ICCD	2011	DBLP DOI BibTeX RDF
1	Guochun Shi, Volodymyr V. Kindratenko, Frederico Pratas, Pedro Trancoso, Michael Gschwind	Application Acceleration with the Cell Broadband Engine.	Computing in Science and Engineering	2010	DBLP DOI BibTeX RDF	PowerXCell 8i processor, chip architecture, data-intensive application architectures, compute-intensive processing, Cell Broadband Engine, chip multiprocessing
1	Valentina Salapura, Michael Gschwind, Jens Knoop (eds.)	19th International Conference on Parallel Architecture and Compilation Techniques (PACT 2010), Vienna, Austria, September 11-15, 2010	PACT	2010	DBLP BibTeX RDF
1	Michael Gschwind, Fred Gustavson, Jan F. Prins	High Performance Computing with the Cell Broadband Engine.	Scientific Programming	2009	DBLP DOI BibTeX RDF
1	Michael Gschwind	Integrated execution: A programming model for accelerators.	IBM Journal of Research and Development	2009	DBLP DOI BibTeX RDF
1	Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri	64-bit prefix adders: Power-efficient topologies and design solutions.	CICC	2009	DBLP DOI BibTeX RDF
1	Michael Gschwind, Alexandru Nicolau, Valentina Salapura, José E. Moreira (eds.)	Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009	ICS	2009	DBLP BibTeX RDF
1	Valentina Salapura, Karthik Ganesan, Alan Gara, Michael Gschwind, James C. Sexton, Robert Walkup	Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
1	Alex Ramírez, Gianfranco Bilardi, Michael Gschwind (eds.)	Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008	Conf. Computing Frontiers	2008	DBLP BibTeX RDF
1	Michael Gschwind	Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor.	ICCD	2008	DBLP DOI BibTeX RDF
1	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
1	Michael Gschwind, David Erb, Sid Manning, Mark Nutter	An Open Source Environment for Cell Broadband Engine System Software.	IEEE Computer	2007	DBLP DOI BibTeX RDF	chip multiprocessors, open source software, multicore processors, Cell Broadband Engine
1	Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki	Synergistic Processing in Cell's Multicore Architecture.	IEEE Micro	2006	DBLP DOI BibTeX RDF	synergistic processing, Cell Broadband Engine, multicore architecture
1	Alexandre E. Eichenberger, Kevin O'Brien, Kathryn M. O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind, Roch Archambault, Yaoqing Gao, Roland Koo	Using advanced compiler technology to exploit the performance of the Cell Broadband EngineTM architecture.	IBM Systems Journal	2006	DBLP DOI BibTeX RDF
1	Michael Gschwind	Chip multiprocessing and the cell broadband engine.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
1	Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind	Optimizing Compiler for the CELL Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Valentina Salapura, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, Dong Chen, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta, Shawn Hall, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos Vranas	Power and performance optimization at the system level.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	BlueGene/L, application performance analysis, application scaling in multiprocessor systems, power/performance efficient systems, power/performance tradeos in systems, chip multiprocessors, supercomputers
1	Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma	Integrated Analysis of Power and Performance for Pipelined Microprocessors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield	New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.	IBM Journal of Research and Development	2003	DBLP DOI BibTeX RDF
1	Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma	Optimizing pipelines for power and performance.	MICRO	2002	DBLP DOI BibTeX RDF
1	Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
1	Michael Gschwind, Erik R. Altman	Precise Exception Semantics in Dynamic Compilation.	CC	2002	DBLP DOI BibTeX RDF
1	Michael Gschwind, Erik R. Altman	Optimization and precise exceptions in dynamic compilation.	SIGARCH Computer Architecture News	2001	DBLP DOI BibTeX RDF
1	Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye	Dynamic Binary Translation and Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures
1	Michael Gschwind, Valentina Salapura, D. Maurer	FPGA prototyping of a RISC processor core for embedded applications.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Michael Gschwind, Erik R. Altman, Sumedh W. Sathaye, Paul Ledak, David Appenzeller	Dynamic and Transparent Binary Translation.	IEEE Computer	2000	DBLP DOI BibTeX RDF
1	Michael Gschwind, Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye	Binary translation and architecture convergence issues for IBM system/390.	ICS	2000	DBLP DOI BibTeX RDF	IBM System/390
1	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind	Execution-Based Scheduling for VLIW Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF	INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION
1	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind	Optimizations and Oracle Parallelism with Dynamic Translation. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	Michael Gschwind	Instruction set selection for ASIP design.	CODES	1999	DBLP DOI BibTeX RDF
1	Valentina Salapura, Michael Gschwind	Hardware/Software Co-Design of a Fuzzy RISC Processor.	DATE	1998	DBLP DOI BibTeX RDF	hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
1	Michael Gschwind, Christian Mautner	Migration from Schematic-Based Designs to a VHDL Synthesis Environment.	FPL	1996	DBLP DOI BibTeX RDF
1	Michael Gschwind, Valentina Salapura	A VHDL Design Methodology for FPGAs.	FPL	1995	DBLP DOI BibTeX RDF
1	Michael Gschwind	FTP Access As a User-defined File System.	Operating Systems Review	1994	DBLP DOI BibTeX RDF	UNIX
1	Michael Gschwind, Christian Mautner	The Design of a Stack-Based Microprocessor.	FPL	1994	DBLP DOI BibTeX RDF
1	Valentina Salapura, Michael Gschwind, Oliver Maischberger	A Fast FPGA Implementation of a General Purpose Neuron.	FPL	1994	DBLP DOI BibTeX RDF
1	Michael Gschwind	Reprogrammable hardware for educational purposes.	SIGCSE	1994	DBLP DOI BibTeX RDF

Publications of "Michael Gschwind" ( http://dblp.L3S.de/Authors/Michael_Gschwind )