Search results for "Michael Kishinevsky"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Satrajit Chatterjee, Michael Kishinevsky	Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics.	Formal Methods in System Design	2012	DBLP DOI BibTeX RDF
1	Marc Galceran Oms, Alexander Gotmanov, Jordi Cortadella, Michael Kishinevsky	Microarchitectural Transformations Using Elasticity.	JETC	2011	DBLP DOI BibTeX RDF
1	Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky	A Scheduling Strategy for Synchronous Elastic Designs.	Fundam. Inform.	2011	DBLP DOI BibTeX RDF
1	Satnam Singh, Barbara Jobstmann, Michael Kishinevsky, Jens Brandt (eds.)	9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011	MEMOCODE	2011	DBLP BibTeX RDF
1	Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov	System interconnect design exploration for embedded MPSoCs.	SLIP	2011	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Alexander Gotmanov, Yuriy Viktorov	Challenges in Verifying Communication Fabrics.	ITP	2011	DBLP DOI BibTeX RDF
1	Alexander Gotmanov, Satrajit Chatterjee, Michael Kishinevsky	Verifying Deadlock-Freedom of Communication Fabrics.	VMCAI	2011	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky	New Region-Based Algorithms for Deriving Bounded Petri Nets.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Petri nets, synthesis, bisimulation, process mining, transition systems, theory of regions
1	Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky	On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics.	Discrete Event Dynamic Systems	2010	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Marc Galceran Oms, Michael Kishinevsky	Elastic systems.	MEMOCODE	2010	DBLP DOI BibTeX RDF
1	Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras	Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing.	NOCS	2010	DBLP DOI BibTeX RDF
1	Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras	Quick formal modeling of communication fabrics to enable verification.	HLDVT	2010	DBLP DOI BibTeX RDF
1	Marc Galceran Oms, Jordi Cortadella, Dmitry Bufistov, Michael Kishinevsky	Automatic microarchitectural pipelining.	DATE	2010	DBLP BibTeX RDF
1	Satrajit Chatterjee, Michael Kishinevsky	Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics.	CAV	2010	DBLP DOI BibTeX RDF
1	Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky	Symbolic performance analysis of elastic systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	A Recursive Paradigm to Solve Boolean Relations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky, Alexander Taubin	Elastic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky	Genet: A Tool for the Synthesis and Mining of Petri Nets.	ACSD	2009	DBLP DOI BibTeX RDF	Synthesis, Mining, Theory of Regions
1	Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky	Scheduling Synchronous Elastic Designs.	ACSD	2009	DBLP DOI BibTeX RDF	Elastic systems, scheduling, optimization
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Timing-driven N-way decomposition.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	logic design, decomposition, timing optimization
1	Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky	Retiming and recycling for elastic systems with early evaluation.	DAC	2009	DBLP DOI BibTeX RDF	early evaluation, elastic systems, optimization
1	Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky	Speculation in elastic systems.	DAC	2009	DBLP DOI BibTeX RDF	elastic designs, protocols, synthesis, speculation
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Variable-latency design by function speculation.	DATE	2009	DBLP BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky	Divide-and-Conquer Strategies for Process Mining.	BPM	2009	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Dmitry Bufistov, Josep Carmona, Jorge Júlvez	Elasticity and Petri Nets.	T. Petri Nets and Other Models of Concurrency	2008	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	A Symbolic Algorithm for the Synthesis of Bounded Petri Nets.	Petri Nets	2008	DBLP DOI BibTeX RDF
1	Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang	A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Jordi Cortadella	Time elastic digital systems and Petri Nets.	ACSD	2008	DBLP DOI BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Michael Kishinevsky	A Region-Based Algorithm for Discovering Petri Nets from Event Logs.	BPM	2008	DBLP DOI BibTeX RDF
1	Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms	Correct-by-construction microarchitectural pipelining.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens	Guest Editors' Introduction: GALS Design and Validation.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	design, synchronous, validation, asynchronous
1	Jordi Cortadella, Michael Kishinevsky	Synchronous Elastic Circuits with Early Evaluation and Token Counterflow.	DAC	2007	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Layout-aware gate duplication and buffer insertion.	DATE	2007	DBLP DOI BibTeX RDF
1	Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar	A general model for performance optimization of sequential systems.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Jordi Cortadella, Bill Grundmann, Sava Krstic, John O'Leary	Synchronous Elastic Circuits.	CSR	2006	DBLP DOI BibTeX RDF
1	Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary	Synchronous Elastic Networks.	FMCAD	2006	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Dominator-based partitioning for delay optimization.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	logic design, timing optimization, logic partitioning
1	Jordi Cortadella, Michael Kishinevsky, Bill Grundmann	Synthesis of synchronous elastic architectures.	DAC	2006	DBLP DOI BibTeX RDF	protocols, synthesis, latency-tolerance, latency-insensitive design
1	Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky	Performance analysis of concurrent systems with early evaluation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Laurent Arditi, Gérard Berry, Michael Kishinevsky	Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs.	FMCAD	2004	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	A recursive paradigm to solve Boolean relations.	DAC	2004	DBLP DOI BibTeX RDF	logic design, decomposition, Boolean relations
1	Gérard Berry, Michael Kishinevsky, Satnam Singh	System Level Design and Verification Using a Synchronous Language.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev	Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	Hardware and Petri Nets: Application to Asynchronous Circuit Design.	ICATPN	2000	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev	Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.	DAC	1999	DBLP DOI BibTeX RDF
1	Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken	CAD Directions for High Performance Asynchronous Circuits.	DAC	1999	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens	Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.	ICCAD	1999	DBLP BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev	Deriving Petri Nets for Finite Transition Systems.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Petri Nets, synthesis, asynchronous systems, concurrent systems, transition systems
1	Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Jordi Cortadella, Luciano Lavagno	The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems.	Journal of Circuits, Systems, and Computers	1998	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial-scan delay fault testing of asynchronous circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	Hazard-free implementation of speed-independent circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten	Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings.	Formal Methods in System Design	1998	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev	Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.	ACSD	1998	DBLP DOI BibTeX RDF	CSC conflicts, Petri Nets, unfoldings, asynchronous design
1	Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev	Asynchronous Interface Specification, Analysis and Synthesis.	DAC	1998	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev	Lazy transition systems: application to timing optimization of asynchronous circuits.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	A region-based theory for state assignment in speed-independent circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev	Coupling Asynchrony and Interrupts: Place Chart Nets.	ICATPN	1997	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.	ASYNC	1997	DBLP DOI BibTeX RDF	combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
1	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
1	Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny	On the Models for Asynchronous Circuit Behaviour with OR Causality.	Formal Methods in System Design	1996	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten	A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.	Application and Theory of Petri Nets	1996	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.	DAC	1996	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	On hazard-free implementation of speed-independent circuits.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev	Synthesizing Petri nets from state-based models.	ICCAD	1995	DBLP DOI BibTeX RDF	Petri nets, Synthesis, Finite State Machines, Asynchronous Circuits, Transition Systems
1	Michael Kishinevsky, Alex Kondratyev, Alexander Taubin	Specification and analysis of self-timed circuits.	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky	Analysis and Identification of Speed-Independent Circuits on an Event Model.	Formal Methods in System Design	1994	DBLP DOI BibTeX RDF
1	Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno	OR Causality: Modelling and Hardware Implementation.	Application and Theory of Petri Nets	1994	DBLP DOI BibTeX RDF
1	Luciano Lavagno, Antonio Lioy, Michael Kishinevsky	Testing redundant asynchronous circuits by variable phase splitting.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Christian D. Nielsen, Michael Kishinevsky	Performance Analysis Based on Timing Simulation.	DAC	1994	DBLP DOI BibTeX RDF
1	Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev	Basic Gate Implementation of Speed-Independent Circuits.	DAC	1994	DBLP DOI BibTeX RDF
1	Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky	Analysis and Identification of Self-Timed Circuits.	Designing Correct Circuits	1992	DBLP BibTeX RDF

Publications of "Michael Kishinevsky" ( http://dblp.L3S.de/Authors/Michael_Kishinevsky )