|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 131 occurrences of 79 keywords
|
|
|
|
|
Results
Found 91 publication records. Showing 91 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design.  |
IEEE Trans. VLSI Syst.  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph |
| 1 | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal |
SPARTAN: a spectral and information theoretic approach to partial-scan. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohit Pandey, Michael L. Bushnell |
Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suresh Kumar Devanathan, Michael L. Bushnell |
Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell |
A Neural Net Branch Predictor to Reduce Power. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey Ayres, Michael L. Bushnell |
Analog Circuit Testing Using Auto Regressive Moving Average Models. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie |
Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique for Structured ASICs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Baozhen Yu, Michael L. Bushnell |
Power Grid Analysis of Dynamic Power Cutoff Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Baozhen Yu, Michael L. Bushnell |
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
power cutoff, standby current, stacking, leakage current, dynamic power |
| 1 | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shweta Chary, Michael L. Bushnell |
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar I. Khan, Michael L. Bushnell |
Aliasing Analysis of Spectral Statistical Response Compaction Techniques. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Suresh Kumar Devanathan, Michael L. Bushnell |
Sequential Spectral ATPG Using the Wavelet Transform and Compaction. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. |
J. Comput. Sci. Technol. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar I. Khan, Michael L. Bushnell |
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal |
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
A Tuturial on the Emerging Nanotechnology Devices. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell |
A New Transitive Closure Algorithm with Application to Redundancy Identification. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
logic redundancy, partial implications, transitive closure, Implication graph |
| 1 | Vishwani D. Agrawal, Michael L. Bushnell |
Electronic Testing for SOC Designers (Tutorial Abstract). (PDF / PS) |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay Mohan, Michael L. Bushnell |
A Code Transition Delay Model for ADC Test. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
Improving path delay testability of sequential circuits. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
Path delay fault simulation of sequential circuits. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. |
J. Electronic Testing |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
| 1 | Madhu K. Iyer, Michael L. Bushnell |
Effect of Noise on Analog Circuit Testing. |
J. Electronic Testing |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, noise analysis |
| 1 | Rajesh Ramadoss, Michael L. Bushnell |
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. |
J. Electronic Testing |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults |
| 1 | Michael L. Bushnell |
Increasing Test Coverage in a VLSI Design Course. |
ITC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A Complete Characterization of Path Delay Faults through Stuck-at Faults. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss |
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
The path-status graph with application to delay fault simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults |
| 1 | Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu |
A non-enumerative path delay fault simulator for sequential circuits. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell |
False-Path Removal Using Delay Fault Simulation. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganapathy Parthasarathy, Michael L. Bushnell |
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. (PDF / PS) |
VTS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell |
On Delay-Untestable Paths and Stuck-Fault Redundancy. (PDF / PS) |
VTS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhu K. Iyer, Michael L. Bushnell |
Effect of Noise on Analog Circuit Testing. (PDF / PS) |
VTS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
Path Delay Testing: Variable-Clock Versus Rated-Clock. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test |
| 1 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel |
Improving a nonenumerative method to estimate path delay fault coverage. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
On variable clock methods for path delay testing of sequential circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Bushnell, John Giraldi |
A Functional Decomposition Method for Redundancy Identification and Test Generation. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
redundancy identification, logic testing, automatic test generation, backtracing |
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
digital circuit testing, test generation, fault models, delay test, path delay faults |
| 1 | Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal |
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinghao Chen, Michael L. Bushnell |
Sequential circuit test generation using dynamic justification equivalence. |
J. Electronic Testing |
1996 |
DBLP DOI BibTeX RDF |
search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification |
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. |
ITC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin |
Redundancy Identification Using Transitive Closure. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Ramadoss, Michael L. Bushnell |
Test generation for mixed-signal devices using signal flow graphs. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits |
| 1 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical path delay fault coverage estimation for synchronous sequential circuits. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation |
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Parallel concurrent path-delay fault simulation using single-input change patterns. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations |
| 1 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
Fault coverage estimation by test vector sampling. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. |
ITC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal |
An adaptive distributed algorithm for sequential circuit test generation. |
EURO-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell |
Functional test generation for path delay faults. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults |
| 1 | Imtiaz P. Shaik, Michael L. Bushnell |
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . |
VTS |
1995 |
DBLP DOI BibTeX RDF |
low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions |
| 1 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
Statistical methods for delay fault coverage analysis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities |
| 1 | Xinghao Chen, Michael L. Bushnell |
Generation of search state equivalence for automatic test pattern generation. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
search state equivalence, current search status, prior search decisions, previously-searched decision spaces, enabling theorem, logic testing, integrated circuit testing, sequential circuits, automatic test pattern generation, automatic testing, search problems, sequential circuit test generation |
| 1 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
| 1 | James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal |
An asynchronous algorithm for sequential circuit test generation on a network of workstations. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
fault list partitioning, multiple test generation processes, parallel algorithms, distributed algorithm, fault diagnosis, logic testing, sequential circuits, mathematical model, automatic test generation, automatic test software, workstation network, asynchronous algorithm, sequential circuit test generation |
| 1 | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
Energy minimization and design for testability. |
J. Electronic Testing |
1994 |
DBLP DOI BibTeX RDF |
neural networks, graph theory, energy minimization, digital testing, Combinational logic circuits |
| 1 | Sandip Parikh, David Sarnoff, Michael L. Bushnell, James Sienicki, Ramakrishnan Ganesh |
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. |
EDAC-ETC-EUROASIC |
1994 |
DBLP BibTeX RDF |
|
| 1 | Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal |
An Efficient Path Delay Fault Coverage Estimator. |
DAC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | James Sienicki, Michael L. Bushnell, Sandip Parikh |
Graphical Methodology Language for CAD Frameworks. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
|
| 1 | Xinghao Chen, Michael L. Bushnell |
Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. |
FTCS |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
Design for Testability for Path Delay faults in Sequential Circuits. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Michael L. Bushnell |
A solvable class of quadratic 0-1 programming. |
Discrete Applied Mathematics |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. |
DAC |
1992 |
DBLP BibTeX RDF |
|
| 1 | John Giraldi, Michael L. Bushnell |
Search State Equivalence for Redundancy Identification and Test Generation. |
ITC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal |
Toward massively parallel automatic test generation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong |
Neural Net and Boolean Satisfiability Models of Logic Circuits. |
IEEE Design & Test of Computers |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | John Giraldi, Michael L. Bushnell |
EST: The New Frontier in Automatic Test-Pattern Generation. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
Automatic Test Generation Using Quadratic 0-1 Programming. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel R. Brasen, Michael L. Bushnell |
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
Polynomial time solvable fault detection problems. |
FTCS |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Bushnell, Stephen W. Director |
Automated design tool execution in the Ulysses design environment. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinghao Chen, Michael L. Bushnell |
A Module Area Estimator for VLSI Layout. |
DAC |
1988 |
DBLP BibTeX RDF |
|
| 1 | Michael L. Bushnell, Stephen W. Director |
ULYSSES - a knowledge-based VLSI design environment. |
AI in Engineering |
1987 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Bushnell, Pierre Haren |
Guest editorial. |
AI in Engineering |
1986 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Bushnell, Stephen W. Director |
VLSI CAD tool integration using the Ulysses environment. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
Ulysses |
Displaying result #1 - #91 of 91 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")