Search results for "Michael S. Schlansker"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael S. Schlansker	Cydra 5.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi	High-performance ethernet-based communications for future multi-core processors.	SC	2007	DBLP DOI BibTeX RDF
1	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder	Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.	MICRO	2006	DBLP DOI BibTeX RDF
1	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker	Fast synchronization for chip multiprocessors.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker	A Distributed Control Path Architecture for VLIW Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Michael S. Schlansker	In Memory of Bob Rau.	MICRO	2003	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Chris J. Newburn	Guest Editors' Introduction.	J. Instruction-Level Parallelism	2001	DBLP BibTeX RDF
1	Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood	Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker	Embedded Computer Architecture and Automation.	IEEE Computer	2001	DBLP DOI BibTeX RDF
1	Shail Aditya, Michael S. Schlansker	ShiftQ: a bufferred interconnect for custom loop accelerators.	CASES	2001	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, B. Ramakrishna Rau	EPIC: Explicititly Parallel Instruction Computing.	IEEE Computer	2000	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker	Embedded Computing: New Directions in Architecture and Automation.	HiPC	2000	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Scott A. Mahlke, Richard Johnson	Control CPR: A Branch Height Reduction Optimization for EPIC Architectures.	PLDI	1999	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Vinod Kathail	Techniques for critical path reduction of scalar programs.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe	Challenges to Combining General-Purpose and Multimedia Processors.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson	Compilers for Instruction-Level Parallelism.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Vinod Kathail, Sadun Anik	Parallelization of Control Recurrences for ILP Processors.	International Journal of Parallel Programming	1996	DBLP BibTeX RDF
1	David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker	Global Predicate Analysis and Its Application to Register Allocation.	MICRO	1996	DBLP BibTeX RDF
1	Richard Johnson, Michael S. Schlansker	Analysis Techniques for Predicated Code.	MICRO	1996	DBLP BibTeX RDF	boolean operand, graph-based data structure, predicated code, program analysis tools, run-time value, compiler optimization, instruction-level parallelism, data flow analysis, compiler analysis
1	Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.	MICRO	1996	DBLP BibTeX RDF	linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling
1	Michael S. Schlansker, Vinod Kathail	Critical path reduction for scalar programs.	MICRO	1995	DBLP DOI BibTeX RDF
1	B. Natarajan, Michael S. Schlansker	Spill-free parallel scheduling of basic blocks.	MICRO	1995	DBLP DOI BibTeX RDF
1	Michael S. Schlansker, Vinod Kathail, Sadun Anik	Height reduction of control recurrences for ILP processors.	MICRO	1994	DBLP DOI BibTeX RDF	back-substitution, blocked back-substitution, control height reduction, parallelism, software pipeline, control dependences, loop optimization, recurrences
1	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
1	Michael S. Schlansker, Vinod Kathail	Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism.	LCPC	1993	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker	Register Allocation for Software Pipelined Loops.	PLDI	1992	DBLP DOI BibTeX RDF
1	Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ASPLOS	1992	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai	Code generation schema for modulo scheduled loops.	MICRO	1992	DBLP DOI BibTeX RDF
1	Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker	Parallelization of WHILE loops on pipelined architectures.	The Journal of Supercomputing	1991	DBLP DOI BibTeX RDF
1	Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker	Parallelization of loops with exits on pipelined architectures.	SC	1990	DBLP BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen	The Cydram 5 Stride-Insensitive Memory System.	ICPP	1989	DBLP BibTeX RDF
1	Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker	Systematically derived instruction sets for high-level language support.	ACM Southeast Regional Conference	1982	DBLP DOI BibTeX RDF	directly interpretable languages, space-time efficiency, syntax and semantics, compilation, interpretation, high-level languages, semantic gap, instruction set design

Publications of "Michael S. Schlansker" ( http://dblp.L3S.de/Authors/Michael_S._Schlansker )