Search results for "Michel Dubois"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jinho Suh, Murali Annavaram, Michel Dubois	MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets.	HPCA	2012	DBLP DOI BibTeX RDF
1	Vanda Luengo, Lucile Vadcard, Jerome Tonetti, Michel Dubois	Diagnostic des connaissances et rétroaction épistémique adaptative en chirurgie.	Revue d'Intelligence Artificielle	2011	DBLP BibTeX RDF
1	Mehrtash Manoochehri, Murali Annavaram, Michel Dubois	CPPC: correctable parity protected cache.	ISCA	2011	DBLP DOI BibTeX RDF
1	Jinho Suh, Mehrtash Manoochehri, Murali Annavaram, Michel Dubois	Soft error benchmarking of L2 caches with PARMA.	SIGMETRICS	2011	DBLP DOI BibTeX RDF
1	Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois	Adaptive and Speculative Slack Simulations of CMPs on CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jianwei Chen, Murali Annavaram, Michel Dubois	SlackSim: a platform for parallel simulations of CMPs on CMPs.	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	Woojin Choi, Seok-Jun Park, Michel Dubois	Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.	T. HiPEAC	2009	DBLP DOI BibTeX RDF
1	Adrian Moga, Michel Dubois	A comparative evaluation of hybrid distributed shared-memory systems.	Journal of Systems Architecture - Embedded Systems Design	2009	DBLP DOI BibTeX RDF
1	Jerome Tonetti, Lucile Vadcard, P. Girard, Michel Dubois, Philippe Merloz, Jocelyne Troccaz	Assessment of a percutaneous iliosacral screw insertion simulator	CoRR	2009	DBLP BibTeX RDF
1	Jianwei Chen, Murali Annavaram, Michel Dubois	SlackSim: a platform for parallel simulations of CMPs on CMPs.	SIGMETRICS Performance Evaluation Review	2009	DBLP DOI BibTeX RDF
1	Jinho Suh, Michel Dubois	Dynamic MIPS rate stabilization in out-of-order processors.	ISCA	2009	DBLP DOI BibTeX RDF	ooo processors, real-time systems, embedded systems, stabilization, variability
1	Jianwei Chen, Murali Annavaram, Michel Dubois	Exploiting Simulation Slack to Improve Parallel Simulation Speed.	ICPP	2009	DBLP DOI BibTeX RDF
1	Viviane Guéraud, Anne Lejeune, Jean-Michel Adam, Michel Dubois, Nadine Mandran	Flexible Environment for Supervising Simulation-Based Learning Situations.	AIED	2009	DBLP DOI BibTeX RDF
1	Viviane Guéraud, Anne Lejeune, Jean-Michel Adam, Michel Dubois, Nadine Mandran	Supervising Distant Simulation-Based Practical Work: Environment and Experimentation.	EC-TEL	2009	DBLP DOI BibTeX RDF	Distant monitoring, Semantic data visualization, Teacher interface, Simulation, Distance Learning, Supervision, Virtual learning environment, Tutoring system, Computer supported learning
1	Xiaogang Qiu, Michel Dubois	The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Michel Dubois, Hyunyoung Lee	STAMP: A universal algorithmic model for next-generation multithreaded machines and systems.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Federico Tajariol, Jean-Michel Adam, Michel Dubois	Seeing the Face and Observing the Actions: The Effects of Nonverbal Cues on Mediated Tutoring Dialogue.	Intelligent Tutoring Systems	2008	DBLP DOI BibTeX RDF	audio-video mediated communication, kinesic cues, ostensive-inferential cues, tutoring dialogue, nonverbal communication
1	Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer (eds.)	High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings	HiPEAC	2008	DBLP BibTeX RDF
1	Jianwei Chen, Michel Dubois, Per Stenström	SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators.	IEEE Micro	2007	DBLP DOI BibTeX RDF	simulation, low-power design, power management, modeling of computer architecture
1	Marc-Eric Bobillier-Chaumon, Michel Dubois, Françoise Sandoz-Guermond	Study of conditions of use of E-services accessible to visually disabled persons	CoRR	2007	DBLP BibTeX RDF
1	Michel Dubois, Hyunyoung Lee, Lan Lin	STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström	Loop-level Speculative Parallelism in Embedded Applications.	ICPP	2007	DBLP DOI BibTeX RDF
1	Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström (eds.)	Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007	Conf. Computing Frontiers	2007	DBLP BibTeX RDF
1	Jaeheon Jeong, Michel Dubois	Cache Replacement Algorithms with Nonuniform Miss Costs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Cache, power, latency, trace-driven simulations, memory system, replacement policy
1	Laxmi N. Bhuyan, Michel Dubois, Will Eatherton (eds.)	Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006	ANCS	2006	DBLP BibTeX RDF
1	Jaeheon Jeong, Per Stenström, Michel Dubois	Simple penalty-sensitive replacement policies for caches.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	cache, memory system, replacement policy, penalty
1	Vanda Luengo, Lucile Vadcard, Michel Dubois, Dima Mufti-Alchawafa	TELEOS : de l'analyse de l'activité professionnelle à la formalisation des connaissances pour un environnement d'apprentissage.	Actes d'IC	2006	DBLP BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
1	Nasir Mohyuddin, Rashed Bhatti, Michel Dubois	Controlling leakage power with the replacement policy in slumberous caches.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	tranquility level, leakage power, replacement policy, drowsy cache
1	Xiaogang Qiu, Michel Dubois	Tolerating Late Memory Traps in Dynamically Scheduled Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Martin Kämpe, Per Stenström, Michel Dubois	Self-correcting LRU replacement policies.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	LRU algorithms, mistake prediction, shadow directories
1	Michel Dubois	Fighting the memory wall with assisted execution.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance
1	Adrian Moga, Michel Dubois	Scalability implications of software-implemented coherence.	Comput. Syst. Sci. Eng.	2003	DBLP BibTeX RDF
1	Jianwei Chen, Michel Dubois, Per Stenström	Integrating complete-system and user-level performance/power simulators: the SimWattch approach.	ISPASS	2003	DBLP DOI BibTeX RDF
1	Jaeheon Jeong, Michel Dubois	Cost-Sensitive Cache Replacement Algorithms.	HPCA	2003	DBLP DOI BibTeX RDF
1	Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda	Shared cache architectures for decision support systems.	Perform. Eval.	2002	DBLP BibTeX RDF
1	Martin Kämpe, Per Stenström, Michel Dubois	The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.	HPCA	2002	DBLP DOI BibTeX RDF	Discrete Fourier Transform, Branch Prediction, Dynamically Scheduled Processors
1	Xiaogang Qiu, Michel Dubois	Towards Virtually-Addressed Memory Hierarchies.	HPCA	2001	DBLP DOI BibTeX RDF
1	Fong Pong, Michel Dubois	Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models.	IEEE Trans. Parallel Distrib. Syst.	2000	DBLP DOI BibTeX RDF	relaxed memory consistency models, delayed consistency, symbolic state model, verification, Shared-memory multiprocessor
1	Jonas Skeppstedt, Michel Dubois	Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines.	J. Parallel Distrib. Comput.	2000	DBLP DOI BibTeX RDF
1	Michel Dubois, Isolde Vial	Multimedia design: the effects of relating multimodal information.	J. Comp. Assisted Learning	2000	DBLP DOI BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	Tolerating Late Memory Traps in ILP Processors.	ISCA	1999	DBLP DOI BibTeX RDF
1	Jaeheon Jeong, Michel Dubois	Optimal Replacements in Caches with Two Miss Costs.	SPAA	1999	DBLP DOI BibTeX RDF
1	Kangwoo Lee, Michel Dubois	Empirical Models of Miss Rates.	Parallel Computing	1998	DBLP DOI BibTeX RDF
1	Fong Pong, Michael C. Browne, Gunes Aybay, Andreas Nowatzyk, Michel Dubois	Design Verification of the S3.mp Cache-Coherent Shared-Memory System.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	competitive-update protocols, write caches, performance evaluation, prefetching, Shared-memory multiprocessors, cache-coherence protocols
1	Fong Pong, Michel Dubois	Formal Verification of Complex Coherence Protocols Using Symbolic State Models.	J. ACM	1998	DBLP DOI BibTeX RDF	state abstraction, state enumeration methods, formal methods, shared-memory multiprocessors, cache coherence protocols
1	Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga	Rapid Hardware Prototyping on RPM-2.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	Options for Dynamic Address Translation in COMAs.	ISCA	1998	DBLP DOI BibTeX RDF
1	Michel Dubois, Christoph Scheurich, Faye A. Briggs	Memory Access Buffering in Multiprocessors.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Michel Dubois, Christoph Scheurich	Retrospective: Memory Access Buffering in Multiprocessors.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Christopher Ho, Heidi E. Ziegler, Michel Dubois	In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs.	SPAA	1998	DBLP DOI BibTeX RDF
1	Adrian Moga, Michel Dubois	The Effectiveness of SRAM Network Caches in Clustered DSMs.	HPCA	1998	DBLP DOI BibTeX RDF
1	Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois	Boosting the Performance of Shared Memory Multiprocessors.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Kangwoo Lee, Woo-Jong Han, Michel Dubois	Bottleneck-Free Interconnect and IO Subsystem in SPAX. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF
1	Jonas Skeppstedt, Michel Dubois	Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	hybrid compiler/hardware prefetching, low-overhead cache miss traps, data prefetching technique, cache coherent multiprocessors, cache miss traps, trap handler, simulated multiprocessor, compiler, multiprocessors, multiprocessing systems
1	Adrian Moga, Michel Dubois, Alain Gefflaut	Hardware Versus Software Implementation of COMA. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	software cache coherence, performance evaluation, distributed shared memory, networks of workstations, COMA
1	Aydin Üresin, Michel Dubois	Effects of Asynchronism on the Convergence Rate of Iterative Algorithms.	J. Parallel Distrib. Comput.	1996	DBLP DOI BibTeX RDF
1	Fong Pong, Michel Dubois	Verification Techniques for Cache Coherence Protocols.	ACM Comput. Surv.	1996	DBLP DOI BibTeX RDF	state representation and expansion, finite state machine, shared-memory multiprocessors, cache coherence, protocol verification
1	Fong Pong, Michel Dubois	Formal Verification of Delayed Consistency Protocols. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF
1	Adrian Moga, Michel Dubois	Performance of Asynchronous Linear Iterations with Random Delays. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	parallel asynchronous algorithms, linear iterative methods, simulation, performance evaluation, multiprocessor systems
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Sequential Hardware Prefetching in Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	Hardware-controlled prefetching, sequential prefetching, performance evaluation, shared-memory multiprocessors, memory consistency models, latency tolerance
1	Fong Pong, Michel Dubois	A New Approach for the Verification of Cache Coherence Protocols.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	symbolic expansion, formal verification, finite state machine, shared-memory multiprocessor, Cache coherence protocol
1	Luiz André Barroso, Michel Dubois	Performance Evaluation of the Slotted Ring Multiprocessor.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	computer architecture, analytical models, shared memory multiprocessors, trace-driven simulation, Cache coherence protocols, slotted ring
1	Michel Dubois, Jonas Skeppstedt, Per Stenström	Essential Misses and Data Traffic in Coherence Protocols.	J. Parallel Distrib. Comput.	1995	DBLP DOI BibTeX RDF
1	Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois	RPM: A Rapid Prototyping Engine for Multiprocessor Systems.	IEEE Computer	1995	DBLP DOI BibTeX RDF
1	Fong Pong, Andreas Nowatzyk, Gunes Aybay, Michel Dubois	Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study.	Euro-Par	1995	DBLP DOI BibTeX RDF
1	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Combined Performance Gains of Simple Cache Protocol Extensions.	ISCA	1994	DBLP DOI BibTeX RDF
1	Fong Pong, Per Stenström, Michel Dubois	An Integrated Methodology for the Verification of Directory-Based Cache Protocols.	ICPP	1994	DBLP BibTeX RDF
1	Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström	The Detection and Elimination of Useless Misses in Multiprocessors.	ISCA	1993	DBLP DOI BibTeX RDF
1	Luiz André Barroso, Michel Dubois	The Performance of Cache-Coherent Ring-based Multiprocessors.	ISCA	1993	DBLP DOI BibTeX RDF
1	Yung-Syau Chen, Michel Dubois	Cache Protocols with Partial Block Invalidations.	IPPS	1993	DBLP BibTeX RDF
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors.	ICPP	1993	DBLP BibTeX RDF
1	Koray Öner, Michel Dubois	Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	SPARC
1	Fong Pong, Michel Dubois	The Verification of Cache Coherence Protocols.	SPAA	1993	DBLP DOI BibTeX RDF
1	Fong Pong, Michel Dubois	Correctness of a Directory-Based Cache Coherence Protocol: Early Experience.	SPDP	1993	DBLP BibTeX RDF
1	Jacqueline Chame, Michel Dubois	Cache Inclusion and Processor Sampling in Multiprocessor Simulations.	SIGMETRICS	1993	DBLP DOI BibTeX RDF
1	Michel Dubois	Special Issue on Memory System Architectures for Scalable Multiprocessors.	J. Parallel Distrib. Comput.	1992	DBLP DOI BibTeX RDF
1	Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner	Scalability Problems in Multiprocessors with Private Caches.	PARLE	1992	DBLP DOI BibTeX RDF
1	Ashfaq A. Khokhar, Michel Dubois	Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems.	IPPS	1992	DBLP BibTeX RDF
1	Michel Dubois, Jin-Chin Wang	Shared Block Contention in a Cache Coherence Protocol.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF
1	Michel Dubois, Faye A. Briggs	The Run-Time Efficiency of Parallel Asynchronous Algorithms.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	software resources, parallel asynchronous algorithms, multiprocessor operating systems, approximate analytical model, software lockout, job queues, shared-memory access conflicts, performance evaluation, performance evaluation, parallel algorithms, data structures, network operating systems, run-time efficiency, run-time efficiency, hardware resources, shared data structures
1	Christoph Scheurich, Michel Dubois	Lockup-free Caches in High-Performance Multiprocessors.	J. Parallel Distrib. Comput.	1991	DBLP DOI BibTeX RDF
1	Michel Dubois, Jin-Chin Wang, Luiz André Barroso, Kangwoo Lee, Yung-Syau Chen	Delayed consistency and its effects on the miss rate of parallel programs.	SC	1991	DBLP DOI BibTeX RDF
1	Jin-Chin Wang, Michel Dubois, Faye A. Briggs	Analytical Modeling for Finite Cache Effects.	ICPP	1991	DBLP BibTeX RDF
1	Luiz André Barroso, Michel Dubois	Cache Coherence on a Slotted Ring.	ICPP	1991	DBLP BibTeX RDF
1	Michel Dubois, Christoph Scheurich	Memory Access Dependencies in Shared-Memory Multiprocessors.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	memory access dependencies, logical concurrency model, pipelining, multiprocessing systems, rules, shared-memory multiprocessors, multiprogramming, storage allocation, multiprocessor architectures, private caches
1	Jin-Chin Wang, Michel Dubois	Performance comparison of cache coherence protocols based on the access burst model.	Comput. Syst. Sci. Eng.	1990	DBLP BibTeX RDF
1	Aydin Üresin, Michel Dubois	Parallel Asynchronous Algorithms for Discrete Data	J. ACM	1990	DBLP DOI BibTeX RDF
1	Michel Dubois, Shreekant S. Thakkar	Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue.	IEEE Computer	1990	DBLP BibTeX RDF
1	Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain	Scalable Shared-Memory Multiprocessor Architectures.	IEEE Computer	1990	DBLP DOI BibTeX RDF
1	Sharad Mehrotra, Chien-Ming Cheng, Kai Hwang, Michel Dubois, Dhabaleswar K. Panda	Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor.	ICPP	1990	DBLP BibTeX RDF
1	Aydin Üresin, Michel Dubois	Asynchronous Iterations with Bounded Delay.	ICPP	1990	DBLP BibTeX RDF
1	Anastasios A. Economides, Michel Dubois	Transient Models of Bus-Based Multiprocessors.	ICPP	1990	DBLP BibTeX RDF
1	Kai Hwang, Michel Dubois, Dhabaleswar K. Panda, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng	OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses.	ICS	1990	DBLP DOI BibTeX RDF
1	Aydin Üresin, Michel Dubois	Sufficient conditions for the convergence of asynchronous iterations.	Parallel Computing	1989	DBLP DOI BibTeX RDF
1	Christoph Scheurich, Michel Dubois	Dynamic Page Migration in Multiprocessors with Distributed Global Memory.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF
1	Michel Dubois	Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	shared interleaved memory, cache-based multiprocessors, general-purpose computing, dynamic instruction mix statistics, performance evaluation, performance, throughput, multiprocessing systems, buffer storage, multitasking, private cache, multiple buses
1	Michel Dubois, Christoph Scheurich, Faye A. Briggs	Synchronization, Coherence, and Event Ordering in Multiprocessors.	IEEE Computer	1988	DBLP DOI BibTeX RDF

Publications of "Michel Dubois" ( http://dblp.L3S.de/Authors/Michel_Dubois )