Search results for "Michiel Steyaert"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Fridolin Michel, Michiel Steyaert	A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans	1D and 2D analog 1.5kHz air-stable organic capacitive touch sensors on plastic foil.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Fridolin Michel, Michiel Steyaert	On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Tom Van Breussegem, Michiel Steyaert	Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans	A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen	Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks.	IEEE Trans. Evolutionary Computation	2011	DBLP DOI BibTeX RDF
1	Tom Redant, Jorg Daniels, Michiel Steyaert, Wim Dehaene	Multiple Event Time-to-Digital Conversion-Based Pulse Digitization for a 250 MHz Pulse Radio Ranging Application.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx	A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Fridolin Michel, Michiel Steyaert	Differential input topologies with immunity to electromagnetic interference.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Maarten Tytgat, Michiel Steyaert, Patrick Reynaert	A 200GHz downconverter in 90nm CMOS.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Hans Meyvaert, Tom Van Breussegem, Michiel Steyaert	A monolithic 0.77W/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Paul Heremans, Wim Dehaene, Michiel Steyaert, Kris Myny, Hagen Marien, Jan Genoe, Gerwin H. Gelinck, Erik van Veenendaal	Circuit design in organic semiconductor technologies.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Lianming Li, Patrick Reynaert, Michiel Steyaert	A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans	DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Michiel Steyaert, Tom Van Breussegem, Hans Meyvaert, Piet Callemeyn, Mike Wens	DC-DC converters: From discrete towards fully integrated CMOS.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Ying Cao, Paul Leroux, Wouter De Cock, Michiel Steyaert	A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converter.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Fridolin Michel, Michiel Steyaert	A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter technique.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Christophe De Roover, Michiel Steyaert	Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx	A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Jorg Daniels, Wim Dehaene, Michiel Steyaert, Andreas Wiesbauer	A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jean-Michel Redoute, Michiel Steyaert	Kuijk Bandgap Voltage Reference With High Immunity to EMI.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jean-Michel Redoute, Michiel Steyaert	EMI-Resistant CMOS Differential Input Stages.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Pieter Palmers, Michiel Steyaert	A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans	An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Jorg Daniels, Wim Dehaene, Michiel Steyaert	All-digital differential VCO-based A/D conversion.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen	Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels	A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Pieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen	Massively multi-topology sizing of analog integrated circuits.	DATE	2009	DBLP BibTeX RDF
1	Kameswaran Vengattaramane, Jan Craninckx, Michiel Steyaert	Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Koen Cornelissens, Michiel Steyaert	Design Considerations for Cascade Delta Sigma ADC's.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert	A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0.13-mu m CMOS.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Hans Danneels, Marian Verhelst, Pieter Palmers, Wim Vereecken, Bruno Boury, Wim Dehaene, Michiel Steyaert, Georges G. E. Gielen	A low-power mixing DAC IR-UWB-receiver.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Jorg Daniels, Wim Dehaene, Michiel Steyaert, Andreas Wiesbauer	A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert	Automated extraction of expert knowledge in analog topology selection and sizing.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert	Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.	DAC	2007	DBLP DOI BibTeX RDF
1	Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen	An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.	DATE	2007	DBLP DOI BibTeX RDF
1	Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen	Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.	DAC	2006	DBLP DOI BibTeX RDF	hierarchical synthesis
1	Raf Schoofs, Michiel Steyaert, Willy M. C. Sansen	A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Vesselin K. Vassilev, Steven Thijs, P. L. Segura, Piet Wambacq, Paul Leroux, Guido Groeseneken, M. I. Natarajan, H. E. Maes, Michiel Steyaert	ESD-RF co-design methodology for the state of the art RF-CMOS blocks.	Microelectronics Reliability	2005	DBLP DOI BibTeX RDF
1	Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene	Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps.	ISLPED	2004	DBLP DOI BibTeX RDF	architectures, ultra-wideband, receiver
1	João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert	Knowledge- and optimization-based design of RF power amplifiers.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Patrick Reynaert, Koen L. R. Mertens, Michiel Steyaert	A state-space behavioral model for CMOS class E power amplifiers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Vesselin K. Vassilev, S. Jenei, Guido Groeseneken, R. Venegas, Steven Thijs, V. De Heyn, M. Natarajan Iyer, Michiel Steyaert, H. E. Maes	High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen	CYCLONE: automated design and layout of RF LC-oscillators.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Carl De Ranter, Michiel Steyaert	Design techniques for low power high bandwidth upconversion in CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	upconversion, low power, CMOS, analog, oscillators, RF design
1	Michiel Steyaert, Peter J. Vancorenland	CMOS: a paradigm for low power wireless?	DAC	2002	DBLP DOI BibTeX RDF	low-power, wireless, CMOS, receivers
1	Jan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen	Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter.	DAC	2002	DBLP DOI BibTeX RDF	simulated annealing, interpolating, flash, A/D converters
1	Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen	Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.	DATE	2002	DBLP DOI BibTeX RDF
1	Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert	Optimization of a fully integrated low power CMOS GPS receiver.	ICCAD	2002	DBLP DOI BibTeX RDF	Systems Application Architecture
1	Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen	A Layout-Aware Synthesis Methodology for RF Circuits.	ICCAD	2001	DBLP BibTeX RDF
1	Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen	CYCLONE: automated design and layout of RF LC-oscillators.	DAC	2000	DBLP DOI BibTeX RDF
1	Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen	Optimal RF design using smart evolutionary algorithms.	DAC	2000	DBLP DOI BibTeX RDF
1	A. Marques, Michiel Steyaert, Willy M. C. Sansen	Theory of PLL fractional-N frequency synthesizers.	Wireless Networks	1998	DBLP DOI BibTeX RDF
1	Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen	A high-level design and optimization tool for analog RF receiver front-ends.	ICCAD	1995	DBLP DOI BibTeX RDF	analog CAD, analog high-level synthesis, RF design and optimization
1	Peter R. Kinget, Michiel Steyaert	Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable Templates.	ISCAS	1994	DBLP BibTeX RDF
1	Michiel Steyaert, Jan Crols, S. Gogaert, Willy M. C. Sansen	Low-voltage Analog CMOS Filter Design.	ISCAS	1993	DBLP BibTeX RDF

Publications of "Michiel Steyaert" ( http://dblp.L3S.de/Authors/Michiel_Steyaert )