Search results for "Michihiro Koibuchi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jose Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho	A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga	An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.	IJNC	2011	DBLP BibTeX RDF
1	Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano	A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	routing, interconnection networks, Ethernet, PC clusters, deadlock avoidance
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	An analytical network performance model for SIMD processor CSX600 interconnects.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A vertical bubble flow network using inductive-coupling for 3-D CMPs.	NOCS	2011	DBLP BibTeX RDF
1	Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano	A Dynamic Link-Width Optimization for Network-on-Chip.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.	ICNC	2011	DBLP DOI BibTeX RDF
1	Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki, Shigeki Yamada	Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network.	Future Internet	2010	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi	Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet.	PDPTA	2010	DBLP BibTeX RDF
1	Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga	An Efficient Path Setup for a Photonic Network-on-Chip.	ICNC	2010	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.	NAS	2010	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.	NAS	2010	DBLP DOI BibTeX RDF	non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through
1	Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi	A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet.	ICPP Workshops	2010	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	Shigeo Urushidani, Shunji Abe, Yusheng Ji, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto	Design of versatile academic infrastructure for multilayer network services.	IEEE Journal on Selected Areas in Communications	2009	DBLP DOI BibTeX RDF
1	Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada	Impact of QoS operations on an experimental testbed network.	Simulation Modelling Practice and Theory	2009	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano	Performance Analysis of ClearSpeed's CSX600 Interconnects.	ISPA	2009	DBLP DOI BibTeX RDF	ClearSpeed, CSX600, performance evaluation, SIMD, NoC
1	Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano	An on/off link activation method for low-power ethernet in PC clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	An On/Off Link Activation Method for Power Regulation in InfiniBand.	PDPTA	2009	DBLP BibTeX RDF
1	Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto	Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3.	ICC	2009	DBLP DOI BibTeX RDF
1	Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki, Masato Yoshimi	Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics.	ISDA	2009	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction router: Yet another low latency on-chip router architecture.	HPCA	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Balanced Dimension-Order Routing for k-ary n-cubes.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi	A link removal methodology for Networks-on-Chip on reconfigurable systems.	FPL	2008	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, Network-on-Chip, routing algorithm, deadlock avoidance, on-chip network
1	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang	Run-time power gating of on-chip routers using look-ahead routing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi	Impact of topology and link aggregation on a PC cluster with Ethernet.	CLUSTER	2008	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano	Three-Dimensional Layout of On-Chip Tree-Based Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada	Architectural Design of Next-Generation Science Information Network.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano	An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	interconnection networks, Adaptive routing, PC clusters, deadlock avoidance, irregular topologies, system area networks, turn model
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	Performance Improvement Methodology for ClearSpeed's CSX600.	ICPP	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
1	Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji	Investigating QoS Performance on a Testbed Network.	ICCCN	2007	DBLP DOI BibTeX RDF
1	Shigeo Urushidani, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Kaori Shimizu, Tomonori Takeda, Ichiro Inoue, Kohei Shiomoto	Layer-1 Bandwidth on Demand Services in SINET3.	GLOBECOM	2007	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	table-lookup routing, interconnection networks, Networks-on-chips, streaming processing, reconfigurable systems, on-chip interconnects
1	Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano	A Parametric Study of Scalable Interconnects on FPGAs.	ERSA	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.	ISCA PDCS	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.	ISPA	2006	DBLP DOI BibTeX RDF
1	Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano	Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.	ICPP	2006	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing.	IEICE Transactions	2005	DBLP BibTeX RDF
1	Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	Path selection algorithm: the strategy for designing deterministic routing from alternative paths.	Parallel Computing	2005	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano	Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	RHiNET, performance evaluation, multicast, interconnection networks, topology, PC clusters, Deterministic routing, system area networks
1	Michihiro Koibuchi, Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato	Enforcing in-order packet delivery in system area networks with adaptive routing.	J. Parallel Distrib. Comput.	2005	DBLP DOI BibTeX RDF
1	Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi	In-Order Packet Delivery in Interconnection Networks using Adaptive Routing.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus.	ICPP	2005	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.	PDPTA	2005	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
1	Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.	IPDPS	2004	DBLP DOI BibTeX RDF	Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing
1	Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura	Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.	EUC	2004	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano	Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies.	ICPP	2003	DBLP DOI BibTeX RDF	RHiNET, interconnection networks, virtual channels, PC clusters, deadlock avoidance, irregular topologies, Deterministic routing, System Area Networks
1	Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano	Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster.	CLUSTER	2003	DBLP DOI BibTeX RDF	RHiNET-2 cluster, Up/Down routing, performance evaluation, interconnection networks, deadlock avoidance, Deterministic routing, System Area Networks
1	Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing.	PDPTA	2002	DBLP BibTeX RDF
1	Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi	Routing Algorithms Based on 2D Turn Model for Irregular Networks. (PDF / PS)	ISPAN	2002	DBLP DOI BibTeX RDF	up/down routing, turn model based routing, traffic balancing, simulation, irregular network, deadlock-free
1	Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano	MMLRU Selection Function: An Output Selection Function on Adaptive Routing.	ISCA PDCS	2001	DBLP BibTeX RDF
1	Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano	L-Turn Routing: An Adaptive Routing in Irregular Networks. (PDF / PS)	ICPP	2001	DBLP DOI BibTeX RDF
1	Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	The impact of output selection function on adaptive routing.	Computers and Their Applications	2001	DBLP BibTeX RDF

Publications of "Michihiro Koibuchi" ( http://dblp.L3S.de/Authors/Michihiro_Koibuchi )