| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama |
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.  |
IEICE Transactions  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama |
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics |
CoRR |
2011 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Watanabe, Masaru Fukushi, Michitaka Kameyama |
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. |
JIP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. |
IEEE Trans. Circuits Syst. Video Techn. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama |
High Performance Tag Singulation for Memory-Less RFID Systems. |
ICC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama |
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama |
Group Testing Based Detection of Web Service DDoS Attackers. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Michitaka Kameyama |
Foreword. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Martin Lukac, Michitaka Kameyama, Marek A. Perkowski |
Adaptive Selection of Intelligent Processing Modules and its Applications. |
IC-AI |
2010 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama |
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama |
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. |
ERSA |
2010 |
DBLP BibTeX RDF |
|
| 1 | Martin Lukac, Marek A. Perkowski, Michitaka Kameyama |
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. |
IEEE Congress on Evolutionary Computation |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama |
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama |
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Keita Tanji, Michitaka Kameyama |
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. |
ERSA |
2009 |
DBLP BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama |
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A low-power FPGA based on autonomous fine-grain power-gating. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Shota Ishihara, Michitaka Kameyama |
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama |
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama |
Memory Allocation for Multi-Resolution Image Processing. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. |
ERSA |
2008 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama |
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. |
ERSA |
2008 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama |
FPGA implementation of a vehicle detection algorithm using three-dimensional information. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture |
| 1 | Michitaka Kameyama |
Special Section on VLSI Technology toward Frontiers of New Market. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tasuku Ito, Michitaka Kameyama |
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. |
Multiple-Valued Logic and Soft Computing |
2007 |
DBLP BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. |
Multiple-Valued Logic and Soft Computing |
2007 |
DBLP BibTeX RDF |
|
| 1 | Tasuku Ito, Michitaka Kameyama |
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Okada, Michitaka Kameyama |
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Sho Ogata, Michitaka Kameyama |
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama |
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi |
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama |
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama |
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Haque Mohammad Munirul, Michitaka Kameyama |
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama |
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama |
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama |
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama |
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama |
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama |
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
data-path design, scheduling, Automatic synthesis, module selection |
| 1 | Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama |
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama |
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama |
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. |
ISMVL |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama |
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. |
ISMVL |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi |
VLSI architecture based on packet data transfer scheme and its application. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama |
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. (PDF / PS) |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama |
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Haque Mohammad Munirul, Michitaka Kameyama |
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Haque Mohammad Munirul, Michitaka Kameyama |
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama |
Multiple-Valued Dynamic Source-Coupled Logic. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama |
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama |
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture |
| 1 | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama |
Fully Source-Coupled Logic Based Multiple-Valued VLSI. (PDF / PS) |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic |
| 1 | Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama |
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. (PDF / PS) |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
Ferroelectric capacitor, multiple-valued current-mode logic circuit, arithmetic operation, full adder |
| 1 | Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama |
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. |
ICRA |
2001 |
DBLP BibTeX RDF |
|
| 1 | Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran |
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. |
ISMVL |
2001 |
DBLP BibTeX RDF |
|
| 1 | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama |
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. |
ISMVL |
2001 |
DBLP BibTeX RDF |
|
| 1 | Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama |
Architecture of a high-performance stereo vision VLSI processor. |
Advanced Robotics |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. |
PRDC |
2000 |
DBLP DOI BibTeX RDF |
dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits |
| 1 | Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama |
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. (PDF / PS) |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama |
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. (PDF / PS) |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
logic-in-memory, communication bottleneck, threshold operation, functional pass gate, DRAM, multiple-valued logic |
| 1 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. (PDF / PS) |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder |
| 1 | Yoshichika Fujioka, Michitaka Kameyama |
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. |
Systems and Computers in Japan |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. (PDF / PS) |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama |
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. (PDF / PS) |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama |
Design and evaluation of a digit-parallel multiple-valued content-addressable memory. |
Systems and Computers in Japan |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama |
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. |
Systems and Computers in Japan |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Michitaka Kameyama |
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. |
ICRA |
1998 |
DBLP BibTeX RDF |
|
| 1 | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama |
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. (PDF / PS) |
ISMVL |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama |
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. (PDF / PS) |
ISMVL |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama |
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. |
Systems and Computers in Japan |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama |
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. (PDF / PS) |
ISMVL |
1997 |
DBLP DOI BibTeX RDF |
cellular logic image processing, template-matching operations, universal literal, threshold operation, multi-layer interconnectio, parallel template-matching, one-transistor-cell, content-addressable memory, cellular logic |
| 1 | Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi |
Author's Reply. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama |
Quaternary Universal-Literal CAM for Cellular Logic Image Processing. (PDF / PS) |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
content addressable memory(CAM), universal literal, threshold programming, floating-gate MOS transistor, multiple-valued logic |
| 1 | Masami Nakajima, Michitaka Kameyama |
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. (PDF / PS) |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
highly parallel circuits, linear digital circuits, multiplicated redundant symbol, k-ary operations, multiple-valued logic |
| 1 | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama |
Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. |
IEICE Transactions |
1995 |
DBLP BibTeX RDF |
|
| 1 | M. Ryu, Michitaka Kameyama |
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. (PDF / PS) |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
highly parallel multiple-valued linear digital system, k-ary operations, extended representation matrices, minimum critical path delay, unary operations, sparse representation matrices, output digit, decomposed unary operations, delays, multivalued logic circuits, sparseness, superposition, code assignment, signal representation |
| 1 | Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama |
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. (PDF / PS) |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models |
| 1 | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama |
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. (PDF / PS) |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic |
| 1 | Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi |
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design |
| 1 | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama |
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. |
ISMVL |
1994 |
DBLP BibTeX RDF |
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| 1 | Masami Nakajima, Michitaka Kameyama |
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. |
ISMVL |
1994 |
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