Search results for "Microprocessors and Microsystems - Embedded Hardware Design"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Fatih Say, Cüneyt F. Bazlamaçci	A reconfigurable computing platform for real time embedded applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Girma S. Tewolde, Darrin M. Hanna, Richard E. Haskell	A modular and efficient hardware architecture for particle swarm optimization algorithm.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Nuno Sebastião, Nuno Roma, Paulo F. Flores	Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	María José Canet, Javier Valls, Vicenc Almenar, José Marín-Roig	FPGA implementation of an OFDM-based WLAN receiver.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Gyu Sang Choi, Ingyu Lee, Mankyu Sung, Choongjae Im	A hybrid SSD with PRAM and NAND Flash memory.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu	Computation and power reduction techniques for H.264 intra prediction.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser	A fast MPSoC virtual prototyping for intensive signal processing applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Prodromos Chatziagorakis, Georgios Ch. Sirakoulis, John N. Lygouras	Design automation of cellular neural networks for data fusion applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Merve Peyic, Hakan Baba, Erdem Guleyuboglu, Ilker Hamzaoglu, Mehmet Keskinoz	A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Zheng Ding, Feng Zhao, Wei Shu, Min-You Wu	Face detection system for SVGA source with hecto-scale frame rate on FPGA board.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Po-Yueh Chen, Chao-Chin Wu, Ying-Jie Jiang	Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Tobias Schumacher, Christian Plessl, Marco Platzner	IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	Low-cost FPGA stereo vision system for real time disparity maps calculation.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Omesh Mutukuda, Andy Ye, Gul Khan	Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Juan Carlos Pichel, Francisco F. Rivera, Marcos Fernández, Aurelio Rodriguez	Optimization of sparse matrix-vector multiplication using reordering techniques on GPUs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar	Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Dongdong Chen, Seok-Bum Ko	A dynamic non-uniform segmentation method for first-order polynomial function evaluation.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Ruymán Reyes, Francisco de Sande	Optimization strategies in different CUDA architectures using llCoMP.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Robert Czerwinski, Dariusz Kania	Area and speed oriented synthesis of FSMs for PAL-based CPLDs.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Antony W. Savich, Medhat Moussa, Shawki Areibi	A scalable pipelined architecture for real-time computation of MLP-BP neural networks.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Jose Rodrigo Sanjurjo, Margarita Amor, Montserrat Bóo, Ramon Doallo	High-performance Monte Carlo radiosity on GPU based on scene partitioning.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee	VLSI-DSP based real time solution of DSC-SRI for an ultrasound system.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Grigorios Mingas, Emmanouil Tsardoulias, Loukas Petrou	An FPGA implementation of the SMG-SLAM algorithm.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Shahin Sanayei Lotfabadi, Andy Ye, Sridhar Krishnan	Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Ramon Doallo, Margarita Amor, Basilio B. Fraguela	Special issue editorial: Exploitation of hardware accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Grigorios Chrysos, Apostolos Dollas, Nikolaos G. Bourbakis	An embedded software-reconfigurable color segmentation architecture for image processing systems.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Uwe Meyer-Bäse, Guillermo Botella Juan, Soumak Mookherjee, Encarnación Castillo, Antonio García	Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	M. Tamagnone, M. Martina, Guido Masera	An application specific instruction set processor based implementation for signal detection in multiple antenna systems.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang	A practical low-latency router architecture with wing channel for on-chip network.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Andrea Marongiu, Paolo Burgio, Luca Benini	Supporting OpenMP on a multi-cluster embedded MPSoC.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	John A. Kalomiros, John N. Lygouras	Design and hardware implementation of a stereo-matching system based on dynamic programming.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng	Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Matthias Bo Stuart, Jens Sparsø	Analytical derivation of traffic patterns in cache-coherent shared-memory systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni	A NoC-based hybrid message-passing/shared-memory approach to CMP design.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Lei Zhang, Meikang Qiu, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Variable assignment and instruction scheduling for processor with multi-module memory.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Gyu Sang Choi, Byung-Won On	Study of the performance impact of a cache buffer in solid-state disks.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Claudia Rusu, Lorena Anghel, Dimiter Avresky	Adaptive inter-layer message routing in 3D networks-on-chip.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Eduardo Tavares, Ermeson Andrade, Bruno Costa e Silva Nogueira, Carlos Araújo, Paulo Roberto Freire Cunha	Energy consumption and execution time estimation of embedded system applications.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro	Finding the optimal tradeoff between area and delay in multiple constant multiplications.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Rishad A. Shafik, Bashir M. Al-Hashimi	Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Zdenka Babic, Aleksej Avramovic, Patricio Bulic	An iterative logarithmic multiplier.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Rabah Sadoun, Adel Belouchrani, El-Bey Bourennane, Ahmed Zerguerras	An FPGA based soft multiprocessor for DNS/DNSSEC authoritative server.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Abdulhadi Shoufan, Nico Huber, H. Gregor Molter	A novel cryptoprocessor architecture for chained Merkle signature scheme.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Wenguo Liu 0001, Alan F. T. Winfield	Open-hardware e-puck Linux extension board for experimental swarm robotics research.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Hongbin Sun, Pengju Ren, Nanning Zheng, Tong Zhang, Tao Li	Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit	Mobile satellite reception with a virtual satellite dish based on a reconfigurable multi-processor architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari	An embedded multi-core biometric identification system.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Giang Nguyen Huong, Yeoul Na, Seon Wook Kim	Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Xianwen Yang, Zheng Li, An Wang, Shengjun Wen	Design research of the DES against power analysis attacks based on FPGA.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	José L. Risco-Martín, J. Manuel Colmenar, David Atienza, José Ignacio Hidalgo	Simulation of high-performance memory allocators.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Man Ho Kim, Suk Lee, Kyung Chang Lee	A fuzzy predictive redundancy system for fault-tolerance of x-by-wire systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Amir Hasanbegovic, Snorre Aunet	Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Muhammad E. S. Elrabaa, Abdelhafid Bouhraoua	A hardwired NoC infrastructure for embedded systems on FPGAs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Malek Naoues, Dominique Noguet, Laurent Alaus, Yves Louët	A common operator for FFT and FEC decoding.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Yixuan Zhang, Randy Wayne Morris Jr., Avinash Karanth Kodi	Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ji Gu, Hui Guo, Patrick Li	An on-chip instruction cache design with one-bit tag for low-power embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Nicolas Huber, M. S. Hromalik-Pouchet, Tobia D. Carozzi, M. P. Gough, A. M. Buckley	Parallel processing speed increase of the one-bit auto-correlation function in hardware.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Wei Song 0002, Doug Edwards	Asynchronous spatial division multiplexing router.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Martti Forsell	Performance comparison of some shared memory organizations for 2D mesh-like NOCs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Jung-Wook Park, Seung-Ho Park, Charles C. Weems, Shin-Dug Kim	A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Anita Tino, Gul N. Khan	Designing power and performance optimal application-specific Network-on-Chip architectures.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería	Filtering directory lookups in CMPs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Antonio Armato, L. Fanucci, Enzo Pasquale Scilingo, Danilo De Rossi	Low-error digital hardware implementation of artificial neuron activation functions and their derivative.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo	A phase adaptive cache hierarchy for SMT processors.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Nikolas Kroupis, Dimitrios Soudris	FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Maurizio Palesi, Shashi Kumar, Radu Marculescu	Network-on-chip architectures and design methodologies.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Licheng Xue, Feng Shi, Weixing Ji, Haroon-Ur-Rashid Khan	3D floorplanning of low-power and area-efficient Network-on-Chip architecture.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen	A study of 3D Network-on-Chip design for data parallel H.264 coding.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira	Real-time fault injection using enhanced on-chip debug infrastructures.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Antoni Roca, José Flich, Federico Silla, José Duato	A low-latency modular switch for CMP systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Uros Legat, Anton Biasizzo, Franc Novak	A compact AES core with on-line error-detection for FPGA applications with modest hardware resources.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Sebastián López	Preface.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ning Ma, Zhonghai Lu, Li-Rong Zheng	System design of full HD MVC decoding on mesh-based multicore NoCs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Ahmad Patooghy, Seyed Ghassem Miremadi, Hamed Tabkhi	A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Amir Muhammad, Michael J. Pont	Comments on: "Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols".	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Pedro Echeverría, Marisa López-Vallejo	Customizing floating-point units for FPGAs: Area-performance-standard trade-offs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich	Virtualizing network-on-chip resources in chip-multiprocessors.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Sanghamitra Roy, Koushik Chakraborty	Exploiting dynamic micro-architecture usage in gate sizing.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Tareq Khan, Khan Wahid	Universal bridge interface for DVP-compatible image sensors.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	J. Manikandan, B. Venkataramani	Design of a real time automatic speech recognition system using Modified One Against All SVM classifier.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Radu Stefan, Kees Goossens	A TDM slot allocation flow based on multipath routing in NoCs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Raija Lehto, Tarja Taurén, Olli Vainio	Recursive FIR filter structures on FPGA.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Sergio Saponara, Luca Fanucci, Marcello Coppola	Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Yiqiong Shi, Bah-Hwee Gwee, Joseph Sylvester Chang	Asynchronous DSP for low-power energy-efficient embedded systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Qinma Kang, Hong He	A novel discrete particle swarm optimization algorithm for meta-task assignment in heterogeneous computing systems.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens	Design and implementation of an operating system for composable processor sharing.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Khalid Latif 0002, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen	Service based communication for MPSoC platform-SegBus.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu	On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi	On chip interconnects for multiprocessor turbo decoding architectures.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Dmitri Vainbrand, Ran Ginosar	Scalable network-on-chip architecture for configurable neural networks.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi	GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin	Hierarchical circuit-switched NoC for multicore video processing.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Chris Jackson, Simon J. Hollis	A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Design of embedded TCAM based longest prefix match search engine.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Christos Georgoulas, Ioannis Andreadis	FPGA based disparity map computation with vergence control.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera	Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Jwu-Sheng Hu, Ming-Tang Lee, Chia-Hsing Yang	An embedded audio-visual tracking and speech purification system on a dual-core processor platform.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Ioakeim G. Georgoudas, P. Kyriakos, Georgios Ch. Sirakoulis, Ioannis Andreadis	An FPGA implemented cellular automaton crowd evacuation model inspired by the electrostatic-induced potential fields.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Nadav Levison, Shlomo Weiss	Branch target buffer design for embedded processors.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF

Publications at "Microprocessors and Microsystems - Embedded Hardware Design"( http://dblp.L3S.de/Venues/Microprocessors_and_Microsystems_-_Embedded_Hardware_Design )