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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 13 keywords
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Results
Found 43 publication records. Showing 43 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.  |
IEICE Transactions  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Power Pulse Generator Design Using Hybrid Logic.  |
IEICE Transactions  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.  |
IEICE Transactions  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu, Wen-Kai Tsai |
An Efficient Architecture of Extended Linear Interpolation for Image Processing.  |
J. Inf. Sci. Eng.  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Chishyan Liaw, Huann-Keng Chiang |
Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction.  |
IEEE Trans. Circuits Syst. Video Techn.  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin |
Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection.  |
IIH-MSP  |
2010 |
DBLP DOI BibTeX RDF |
object detection, background modeling |
| 1 | Ming-Hwa Sheu, Wen-Kai Tsai, Chuang-Chun Hu, Chun-Heng Tsao |
Fast Texture-Based Object Tracking Algorithm on Embedded Platform.  |
FCST  |
2010 |
DBLP DOI BibTeX RDF |
texture, object tracking |
| 1 | Shyue-Wen Yang, Ming-Hwa Sheu, Jun-Jie Lin, Chuang-Chun Hu, Tzu-Hsiung Chen, Shau-Yin Tseng |
Parallel 3-Pixel Labeling Method and its Hardware Architecture Design.  |
IAS  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang |
Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1).  |
ISCAS  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Kai Tsai, Ming-Hwa Sheu, Ching-Lung Su, Jun-Jie Lin, Shau-Yin Tseng |
Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform.  |
IIH-MSP  |
2009 |
DBLP DOI BibTeX RDF |
object detetion, object tracking |
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw |
High-performance very large scale integration architecture design for various-ratio image scaling.  |
J. Electronic Imaging  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Hon Lin, Ming-Hwa Sheu |
Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection.  |
IEICE Transactions  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Complexity Dual-Mode Pulse Generator Designs.  |
IEICE Transactions  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang |
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1).  |
IEICE Transactions  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Hon Lin, Ming-Hwa Sheu |
VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection.  |
IEEE Trans. on Circuits and Systems  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu |
The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing.  |
ISCAS  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Zeng-Chuan Wu, Jia-Yi Tu, Chia-Hung Chen |
A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing.  |
ICESS  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei, Chishyan Liaw |
A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information.  |
IEICE Transactions  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen |
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection.  |
SiPS  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multipliers Using Enhenced Row Bypassing Schemes.  |
SiPS  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai |
Fast Fair Crossbar Scheduler for On-chip Router.  |
ISCAS  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Zeng-Chuan Wu, Wen-Kai Tsai, Ming-Hwa Sheu, Huann-Keng Chiang |
The VLSI Design of Winscale for Digital Image Scaling.  |
IIH-MSP  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-che Chen |
Film-to-Video Conversion with Scene Cut Detection.  |
ICICIC  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu |
Automatic Generation of Programmable Parallel CRC & Scrambler Designs.  |
SiPS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.  |
APCCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu |
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).  |
APCCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei |
The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.  |
APCCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw |
The VLSI design of de-interlacing with scene change detection.  |
ISCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
A high speed and energy efficient full adder design using complementary & level restoring carry logic.  |
ISCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw |
Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.  |
PCM  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsien-Huang P. Wu, Ming-Hwa Sheu, Tung-Yu Yang |
Directional interpolation for field-sequential stereoscopic video.  |
ISCAS  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu |
VLSI architecture design for a fast parallel label assignment in binary image.  |
ISCAS  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu |
A Fast Additive Normalization Method for Exponential Computation.  |
DSD  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Hwa Sheu, Su-Hon Lin |
Fast design approach for implementing the approximate squaring function.  |
APCCAS  |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo |
A Systematic Approach for Parallel CRC Computations.  |
J. Inf. Sci. Eng.  |
2001 |
DBLP BibTeX RDF |
|
| 1 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu |
VLSI architecture of extended in-place path metric update for Viterbi decoders.  |
ISCAS  |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh |
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.  |
ISCAS  |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu |
High-speed generation of LFSR signatures.  |
Asian Test Symposium  |
2000 |
DBLP DOI BibTeX RDF |
high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences |
| 1 | Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu |
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.  |
ISCAS  |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Hwa Sheu, Yuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee |
The determination of the cycle length in high level synthesis.  |
Integration  |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu |
A High Throughput-Rate Architecture for 8*8 2-D DCT.  |
ISCAS  |
1993 |
DBLP BibTeX RDF |
|
| 1 | Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu |
An Expandable Chip Desing for Gray-scale Morphological Operations.  |
ISCAS  |
1993 |
DBLP BibTeX RDF |
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