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Publications of "Ming-Hwa Sheu" ( http://dblp.L3S.de/Authors/Ming-Hwa_Sheu )

  Author page on DBLP  Author page in RDF  Community of Ming-Hwa Sheu in ASPL-2

Publication years (Num. hits)
1993-2006 (20) 2007-2009 (15) 2010-2012 (8)
Publication types (Num. hits)
article(14) inproceedings(29)
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The graphs summarize 14 occurrences of 13 keywords

Results
Found 43 publication records. Showing 43 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. Search on Bibsonomy IEICE Transactions The full citation details ... 2010 DBLP  BibTeX  RDF
1Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu Low Power Pulse Generator Design Using Hybrid Logic. Search on Bibsonomy IEICE Transactions The full citation details ... 2010 DBLP  BibTeX  RDF
1Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. Search on Bibsonomy IEICE Transactions The full citation details ... 2010 DBLP  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu, Wen-Kai Tsai An Efficient Architecture of Extended Linear Interpolation for Image Processing. Search on Bibsonomy J. Inf. Sci. Eng. The full citation details ... 2010 DBLP  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Chishyan Liaw, Huann-Keng Chiang Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Wen-Kai Tsai, Ming-Hwa Sheu, Chung-Chi Lin Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection. Search on Bibsonomy IIH-MSP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF object detection, background modeling
1Ming-Hwa Sheu, Wen-Kai Tsai, Chuang-Chun Hu, Chun-Heng Tsao Fast Texture-Based Object Tracking Algorithm on Embedded Platform. Search on Bibsonomy FCST The full citation details ... 2010 DBLP  DOI  BibTeX  RDF texture, object tracking
1Shyue-Wen Yang, Ming-Hwa Sheu, Jun-Jie Lin, Chuang-Chun Hu, Tzu-Hsiung Chen, Shau-Yin Tseng Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. Search on Bibsonomy IAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Yuan-Ching Kuo, Su-Hon Lin, Ming-Hwa Sheu, Jia-You Wu, Peng-Siang Wang Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1). Search on Bibsonomy ISCAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Wen-Kai Tsai, Ming-Hwa Sheu, Ching-Lung Su, Jun-Jie Lin, Shau-Yin Tseng Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform. Search on Bibsonomy IIH-MSP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF object detetion, object tracking
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw High-performance very large scale integration architecture design for various-ratio image scaling. Search on Bibsonomy J. Electronic Imaging The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Su-Hon Lin, Ming-Hwa Sheu Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection. Search on Bibsonomy IEICE Transactions The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu Low Complexity Dual-Mode Pulse Generator Designs. Search on Bibsonomy IEICE Transactions The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1). Search on Bibsonomy IEICE Transactions The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Su-Hon Lin, Ming-Hwa Sheu VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Zeng-Chuan Wu The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Zeng-Chuan Wu, Jia-Yi Tu, Chia-Hung Chen A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing. Search on Bibsonomy ICESS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei, Chishyan Liaw A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information. Search on Bibsonomy IEICE Transactions The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. Search on Bibsonomy SiPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu Low Power Multipliers Using Enhenced Row Bypassing Schemes. Search on Bibsonomy SiPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai Fast Fair Crossbar Scheduler for On-chip Router. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Zeng-Chuan Wu, Wen-Kai Tsai, Ming-Hwa Sheu, Huann-Keng Chiang The VLSI Design of Winscale for Digital Image Scaling. Search on Bibsonomy IIH-MSP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-che Chen Film-to-Video Conversion with Scene Cut Detection. Search on Bibsonomy ICICIC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu Automatic Generation of Programmable Parallel CRC & Scrambler Designs. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chih-Jen Wei The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw The VLSI design of de-interlacing with scene change detection. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho A high speed and energy efficient full adder design using complementary & level restoring carry logic. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. Search on Bibsonomy PCM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Hsien-Huang P. Wu, Ming-Hwa Sheu, Tung-Yu Yang Directional interpolation for field-sequential stereoscopic video. Search on Bibsonomy ISCAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu VLSI architecture design for a fast parallel label assignment in binary image. Search on Bibsonomy ISCAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu A Fast Additive Normalization Method for Exponential Computation. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Ming-Hwa Sheu, Su-Hon Lin Fast design approach for implementing the approximate squaring function. Search on Bibsonomy APCCAS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo A Systematic Approach for Parallel CRC Computations. Search on Bibsonomy J. Inf. Sci. Eng. The full citation details ... 2001 DBLP  BibTeX  RDF
1Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu VLSI architecture of extended in-place path metric update for Viterbi decoders. Search on Bibsonomy ISCAS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. Search on Bibsonomy ISCAS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu High-speed generation of LFSR signatures. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences
1Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. Search on Bibsonomy ISCAS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
1Ming-Hwa Sheu, Yuan-Long Jeang, Jhing-Fa Wang, Jau-Yien Lee The determination of the cycle length in high level synthesis. Search on Bibsonomy Integration The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
1Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu A High Throughput-Rate Architecture for 8*8 2-D DCT. Search on Bibsonomy ISCAS The full citation details ... 1993 DBLP  BibTeX  RDF
1Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu An Expandable Chip Desing for Gray-scale Morphological Operations. Search on Bibsonomy ISCAS The full citation details ... 1993 DBLP  BibTeX  RDF
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