Search results for "Miquel Pericàs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	BSArc: blacksmith streaming architecture for HPC accelerators.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
1	Tassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	PPMC: A Programmable Pattern Based Memory Controller.	ARC	2012	DBLP DOI BibTeX RDF
1	Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, Mateo Valero	Assessing Accelerator-Based HPC Reverse Time Migration.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	Reverse time migration, Cell/B.E., geophysics, FPGA, GPU, accelerators
1	Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool.	FPT	2011	DBLP DOI BibTeX RDF
1	Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators.	FPL	2010	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	Power-efficient VLIW design using clustering and widening.	IJES	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero	A Two-Level Load/Store Queue Based on Execution Locality.	ISCA	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero	Vectorized AES Core for High-throughput Secure Environments.	VECPAR	2008	DBLP DOI BibTeX RDF	Encryption, Parallel and Distributed Computing
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A Flexible Heterogeneous Multi-Core Architecture.	PACT	2007	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A decoupled KILO-instruction processor.	HPCA	2006	DBLP DOI BibTeX RDF
1	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
1	Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum	An asymmetric clustered processor based on value content.	ICS	2005	DBLP DOI BibTeX RDF	content aware architectures, cluster architectures
1	Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez	Chained In-Order/Out-of-Order DoubleCore Architecture.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero	Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero	Decoupled State-Execute Architecture.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	High-performance and low-power VLIW cores for numerical computations.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	with Wide Functional Units.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero	An Optimized Front-End Physical Register File with Banking and Writeback Filtering.	PACS	2004	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.	ISHPC	2003	DBLP DOI BibTeX RDF

Publications of "Miquel Pericàs" ( http://dblp.L3S.de/Authors/Miquel_Pericàs )