Search results for "Mircea R. Stan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Edmund Cheng	Temperature-Aware Architecture: Lessons and Opportunities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron	Scaling with Design Constraints: Predicting the Future of Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	big chips, cooling solution, power, system architecture, processor architecture, temperature, technology scaling, area, design constraints, many-core processor
1	Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan	Modeling and analyzing NBTI in the presence of Process Variation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan	Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM).	ISLPED	2011	DBLP BibTeX RDF
1	Adam C. Cabe, Mircea R. Stan	Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Mehdi Kabir, Mircea R. Stan, Stuart A. Wolf, Ryan B. Comes, Jiwei Lu	RAMA: a self-assembled multiferroic magnetic QCA for low power systems.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Clinton Wills Smullen IV, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan	Relaxing non-volatility for fast and energy-efficient STT-RAM caches.	HPCA	2011	DBLP DOI BibTeX RDF
1	Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan	The STeTSiMS STT-RAM simulation and modeling system.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun	Improving SRAM Vmin and yield by using variation-aware BTI stress.	CICC	2010	DBLP DOI BibTeX RDF
1	Adam C. Cabe, Zhenyu Qi, Mircea R. Stan	Stacking SRAM banks for ultra low power standby mode operation.	DAC	2010	DBLP DOI BibTeX RDF	stacked SRAM, low-power memory
1	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
1	Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan	FlashPower: A detailed power model for NAND flash memory.	DATE	2010	DBLP BibTeX RDF
1	Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan	Temperature-to-power mapping.	ICCD	2010	DBLP DOI BibTeX RDF
1	Sudhanva Gurumurthi, Sriram Sankar, Mircea R. Stan	Using Intradisk Parallelism to Build Energy-Efficient Storage Systems.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Sriram Sankar, Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan	Sensitivity-Based Optimization of Disk Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan	Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay.	ISQED	2009	DBLP DOI BibTeX RDF
1	Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan	Differentiating the roles of IR measurement and simulation for power and temperature-aware design.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Dincer Unluer, Avik Ghosh, Frank S. C. Tseng	Graphene Devices, Interconnect and Circuits - Challenges and Opportunities.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan	Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan	Intra-disk Parallelism: An Idea Whose Time Has Come.	ISCA	2008	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Mircea R. Stan	NBTI resilient circuits using adaptive body biasing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	reliability, body bias, nbti
1	Wei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron	Many-core design from a thermal perspective.	DAC	2008	DBLP DOI BibTeX RDF	many-core design, thermal design power, performance, temperature
1	Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan	Sensitivity Based Power Management of Enterprise Storage Systems.	MASCOTS	2008	DBLP BibTeX RDF
1	Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan	Designing CMOS/molecular memories while considering device parameter variations.	JETC	2007	DBLP DOI BibTeX RDF	CMOS, nanotechnology, molecular electronics
1	Zhijian Lu, Wei Huang, Mircea R. Stan, Kevin Skadron, John Lach	Interconnect Lifetime Prediction for Reliability-Aware Systems.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan	Multi-Dimensional Circuit and Micro-Architecture Level Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
1	Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan	Structured and tuned array generation (STAG) for high-performance random logic.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	programmable logic arrays (PLAs), design automation
1	Yan Zhang, Mircea R. Stan	Temperature-aware circuit design using adaptive body biasing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	adaptive body biasing, temperature-aware design
1	Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan	SODA: Sensitivity Based Optimization of Disk Architecture.	DAC	2007	DBLP DOI BibTeX RDF
1	Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, Mircea R. Stan	HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu (eds.)	Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006	ISLPED	2006	DBLP BibTeX RDF
1	Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour	Design approaches for hybrid CMOS/molecular memory based on experimental device data.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
1	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler	Hybrid CMOS/Molecular Electronic Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron	Procrastinating voltage scheduling with discrete frequency sets.	DATE	2006	DBLP DOI BibTeX RDF
1	Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron	Improved Thermal Management with Reliability Banking.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Dynamic thermal/reliability management, Analytical and simulation techniques, Modeling, Performability, Electromigration
1	Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan	The need for a full-chip and package thermal model for thermally optimized IC designs.	ISLPED	2005	DBLP DOI BibTeX RDF	leakage, package, thermal model, temperature-aware design
1	Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan	Optimal procrastinating voltage scheduling for hard real-time systems.	DAC	2005	DBLP DOI BibTeX RDF	power management, dynamic voltage scaling, real-time scheduling, optimization algorithm
1	Yan Zhang, Travis N. Blalock, Mircea R. Stan	A three-level toggle-avoid bus signaling scheme.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Sivakumar Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron	Monitoring Temperature in FPGA based SoCs.	ICCD	2005	DBLP DOI BibTeX RDF
1	Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, David Tarjan	Temperature-aware microarchitecture: Modeling and implementation.	TACO	2004	DBLP DOI BibTeX RDF	Dynamic compact thermal models, fetch gating, dynamic voltage scaling, feedback control, dynamic thermal management
1	Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea R. Stan	Power-Aware Branch Prediction: Characterization and Design.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking
1	Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan	Large-signal two-terminal device model for nanoelectronic circuit analysis.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Yan Zhang	Perfect 3-Limited-Weight Code for Low Power I/O.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Fatih Hamzaoglu, David Garrett	Non-Manhattan maze routing.	SBCCI	2004	DBLP DOI BibTeX RDF	Manhattan routing, multi-layer routing, non-Manhattan routing, global routing, local routing
1	Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy	Compact thermal modeling for temperature-aware design.	DAC	2004	DBLP DOI BibTeX RDF	temperature-aware computing, reliability, leakage, thermal model, temperature-aware design, power-aware design
1	Lei He, Weiping Liao, Mircea R. Stan	System level leakage reduction considering the interdependence of temperature and leakage.	DAC	2004	DBLP DOI BibTeX RDF	microarchitecture, leakage power, temperature
1	Matthew M. Ziegler, Mircea R. Stan	A Unified Design Space for Regular Parallel Prefix Adders.	DATE	2004	DBLP DOI BibTeX RDF	Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
1	Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron	State-Preserving vs. Non-State-Preserving Leakage Control in Caches.	DATE	2004	DBLP DOI BibTeX RDF
1	Mircea R. Stan	Systolic counters with unique zero state.	ISCAS	2004	DBLP BibTeX RDF
1	Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron	Interconnect lifetime prediction under dynamic stress for reliability-aware design.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron	Alloyed Branch History: Combining Global and Local Branch History for Robust Performance.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Kevin Skadron, Marco Barcella, Wei Huang, Karthik Sankaranarayanan, Sivakumar Velusamy	HotSpot: a dynamic compact thermal model at the processor-architecture level.	Microelectronics Journal	2003	DBLP DOI BibTeX RDF
1	Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan	Temperature-Aware Computer Systems: Opportunities and Challenges.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Kevin Skadron	Guest Editors' Introduction: Power-Aware Computing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan	Temperature-Aware Microarchitecture. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Matthew M. Ziegler, Mircea R. Stan	The CMOS/nano interface from a circuits perspective.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Marco Barcella	MTCMOS with outer feedback (MTOF) flip-flops.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron	Reducing Multimedia Decode Power using Feedback Control.	ICCD	2003	DBLP DOI BibTeX RDF
1	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Mircea R. Stan	CMOS Circuits with Subvolt Supply Voltages.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
1	Fatih Hamzaoglu, Mircea R. Stan	Circuit-level techniques to control gate leakage for sub-100nm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, MTCMOS, gate leakage, domino circuits
1	Zhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan, John Lach, Kevin Skadron	Control-theoretic dynamic frequency and voltage scaling for multimedia workloads.	CASES	2002	DBLP DOI BibTeX RDF	control theoretic, frequency/voltage scaling, multimedia, real-time, high performance, feedback control, low energy, power aware
1	Mircea R. Stan, Avishek Panigrahi	The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits.	DATE	2002	DBLP DOI BibTeX RDF
1	Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, Mircea R. Stan	Power Issues Related to Branch Prediction.	HPCA	2002	DBLP DOI BibTeX RDF	Performance, Power, Energy, Branch Prediction
1	Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan	Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.	HPCA	2002	DBLP DOI BibTeX RDF	thermal modeling and management, formal feedback control theory, performance, power, microprocessors
1	Matthew M. Ziegler, Mircea R. Stan	A Case for CMOS/nano co-design.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Mircea R. Stan	Low-power CMOS with subvolt supply voltages.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan	A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Joshua L. Garrett, Mircea R. Stan	Active threshold compensation circuit for improved performance in cooled CMOS systems.	ISCAS	2001	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan, Alvar Dean	Challenges in clockgating for a low power ASIC methodology.	ISLPED	1999	DBLP DOI BibTeX RDF	clockgating, clocktree, low power, physical design
1	Mircea R. Stan	Optimal Voltages and Sizing for Low Power.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac	Long and Fast Up/Down Counters.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Binary counter, constant time counter, serial counter, up/down counter, prescaler, parallel counter
1	Mircea R. Stan	Low threshold CMOS circuits with low standby current.	ISLPED	1998	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan	Low power architecture of the soft-output Viterbi algorithm.	ISLPED	1998	DBLP DOI BibTeX RDF	SOVA, VA, low power, turbo codes
1	Mircea R. Stan, Wayne P. Burleson	Low-power encodings for global communication in CMOS VLSI.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan	Power reduction techniques for a spread spectrum based correlator.	ISLPED	1997	DBLP DOI BibTeX RDF
1	Mircea R. Stan	Synchronous Up/Down Counter with Clock Period Independent of Counter Size.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	up/down counters, constant time counters, prescalers
1	Mircea R. Stan, Wayne P. Burleson	Two dimensional codes for low power.	ISLPED	1996	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
1	Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen	Analog VLSI for robot path planning.	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF

Publications of "Mircea R. Stan" ( http://dblp.L3S.de/Authors/Mircea_R._Stan )