Search results for "Mitaro Namiki"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano	A Leakage Efficient Data TLB Design for Embedded Processors.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano	A Leakage Efficient Instruction TLB Design for Embedded Processors.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Mikiko Sato, Yuji Sato, Mitaro Namiki	Acceleration experiment of genetic computations for sudoku solution on multi-core processors.	GECCO (Companion)	2011	DBLP DOI BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Array: A highly energy efficient reconfigurable accelerator.	FPT	2011	DBLP DOI BibTeX RDF
1	Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo	Geyser-2: The second prototype CPU with fine-grained run-time power gating.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Hiroki Manabe, Susumu Kanemune, Mitaro Namiki, Yoshiaki Nakano	CS Unplugged Assisted by Digital Materials for Handicapped People at Schools.	ISSEP	2011	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	Adaptive power gating for function units in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
1	Mikiko Sato, Yuji Sato, Mitaro Namiki	Proposal of a multi-core processor architecture for effective evolutionary computation.	GECCO	2010	DBLP DOI BibTeX RDF	genegic algorithms, parallel computing, evolutionary computation, multi-core processor
1	Mikiko Sato, Yuji Sato, Mitaro Namiki	Proposal of a multi-core processor from the viewpoint of evolutionary computation.	IEEE Congress on Evolutionary Computation	2010	DBLP DOI BibTeX RDF
1	Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki	Reducing instruction TLB's leakage power consumption for embedded processors.	Green Computing Conference	2010	DBLP DOI BibTeX RDF
1	Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara	Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.	ICPP	2009	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Tomohiro Nishida, Susumu Kanemune, Yukio Idosaka, Mitaro Namiki, Tim Bell, Yasushi Kuno	A CS unplugged design pattern.	SIGCSE	2009	DBLP DOI BibTeX RDF	kinaesthetic learning, pedagogical design patterns
1	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
1	Jun Kanai, Mitaro Namiki, Kuniyasu Suzaki, Toshiki Yagi	Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX".	PDPTA	2007	DBLP BibTeX RDF
1	Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo	A Model of Implementable SMT Processor on FPGA.	PDPTA	2006	DBLP BibTeX RDF
1	Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo	Towards Reconfigurable Cache Memory for a Multithreaded Processor.	PDPTA	2006	DBLP BibTeX RDF
1	Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki	Implementation of PC Cluster System with Memory Mapped File by Commodity OS.	PDPTA	2006	DBLP BibTeX RDF
1	Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki	Development of a Thread Scheduler for SMT Processor Architecture.	PDPTA	2005	DBLP BibTeX RDF
1	Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo	A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.	PDPTA	2005	DBLP BibTeX RDF
1	Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo	Dynamic Allocation of Physical Register Banks for an SMT Processor.	PDPTA	2004	DBLP BibTeX RDF
1	Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki	Implementation and Evaluation of a Thread Library for Multithreaded Architecture.	PDPTA	2003	DBLP BibTeX RDF
1	Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki	A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.	PDPTA	2003	DBLP BibTeX RDF
1	Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki	Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.	PDPTA	2003	DBLP BibTeX RDF

Publications of "Mitaro Namiki" ( http://dblp.L3S.de/Authors/Mitaro_Namiki )