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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 9 keywords
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Results
Found 25 publication records. Showing 25 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Mohammad Hosseinabady, Jose Luis Nunez-Yanez |
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.  |
IET Computers & Digital Techniques  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Antonio Marcello Coppola |
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, José L. Núñez-Yáñez |
SystemC Architectural Transaction Level Modelling for Large NoCs. |
FDL |
2010 |
DBLP BibTeX RDF |
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| 1 | Mohammad Hosseinabady, José L. Núñez-Yáñez |
Effective modelling of large NoCs using SystemC. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, José L. Núñez-Yáñez |
Run-time resource management in fault-tolerant network on reconfigurable chips. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi |
A Selective Trigger Scan Architecture for VLSI Testing. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power |
| 1 | Mohammad Hosseinabady, José L. Núñez-Yáñez |
Fault-tolerant dynamically reconfigurable NoC-based SoC. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan |
Fault tolerant bit parallel finite field multipliers using LDPC codes. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi |
Low test application time resource binding for behavioral synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
CDFG, high-level synthesis, Testability, test synthesis |
| 1 | Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi |
Simultaneous Reduction of Dynamic and Static Power in Scan Structures |
CoRR |
2007 |
DBLP BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi |
Low overhead DFT using CDFG by modifying controller. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan |
Single Event Upset Detection and Correction. |
ICIT |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi |
A UML Based System Level Failure Rate Assessment Technique for SoC Designs. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi |
Using the inter- and intra-switch regularity in NoC switch testing. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi |
An Analytical Model for Reliability Evaluation of NoC Architectures. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale |
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi |
Scan-Based Structure with Reduced Static and Dynamic Power Consumption. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto |
Single-Event Upset Analysis and Protection in High Speed Circuits. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi |
A concurrent testing method for NoC switches. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi |
TED+: a data structure for microprocessor verification. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi |
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi |
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. |
VLSI-SOC |
2003 |
DBLP BibTeX RDF |
|
| 1 | Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi |
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
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