Search results for "Mohammad M. Mansour"

Found 18 publication records. Showing 18 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Mohammad M. Mansour, Liang-Gee Chen, Wonyong Sung	Trends in Design and Implementation of Signal Processing Systems [In the Spotlight].	IEEE Signal Process. Mag.	2011	DBLP DOI BibTeX RDF
1	Hady Zeineddine, Mohammad M. Mansour, R. Puri	Construction and Hardware-Efficient Decoding of Raptor Codes.	IEEE Transactions on Signal Processing	2011	DBLP DOI BibTeX RDF
1	Hady Zeineddine, Mohammad M. Mansour	Reconfigurable decoder architectures for Raptor codes.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour	Parallel lookahead algorithms for pruned interleavers.	IEEE Transactions on Communications	2009	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour	A Parallel Pruned Bit-Reversal Interleaver.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour	A parallel architecture for 3GPP2/UMB turbo interleavers.	ICASSP	2009	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour	Optimized Architecture for Computing Zadoff-Chu Sequences with Application to LTE.	GLOBECOM	2009	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour	Parallel channel interleavers for 3GPP2/UMB.	SiPS	2008	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	turbo-decoding message-passing algorithm, VLSI decoder architectures, LDPC codes, Ramanujan graphs
1	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	VLSI architectures for SISO-APP decoders.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	High-throughput LDPC decoders.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Parameterized Macrocells with Accurate Delay Models for Core-Based Designs.	ISQED	2003	DBLP DOI BibTeX RDF
1	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Amit Mehrotra	Efficient core designs based on parameterized macrocells with accurate delay models.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	Architecture-aware low-density parity-check codes.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	Low-power VLSI decoder architectures for LDPC codes.	ISLPED	2002	DBLP DOI BibTeX RDF	BCJR algorithm, lower power architectures, LDPC codes
1	Mohammad M. Mansour, Naresh R. Shanbhag	Simplified current and delay models for deep submicron CMOS digital circuits.	ISCAS	2002	DBLP DOI BibTeX RDF

Publications of "Mohammad M. Mansour" ( http://dblp.L3S.de/Authors/Mohammad_M._Mansour )