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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 6 keywords
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Results
Found 20 publication records. Showing 20 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
A resilient architecture for low latency communication in shared-L1 processor clusters.  |
DATE  |
2012 |
DBLP BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini |
A distributed and topology-agnostic approach for on-line NoC testing. |
NOCS |
2011 |
DBLP BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini |
ReliNoC: A reliable network for priority-based on-chip communication. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini |
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini |
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold |
| 1 | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
A new physical routing approach for robust bundled signaling on NoC links. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing |
| 1 | Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini |
A floorplan-aware interactive tool flow for NoC design and synthesis. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi |
Graph based test case generation for TLM functional verification. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Assertion Synthesis, Assertion Unification, Online Testing |
| 1 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
On-Chip Verification of NoCs Using Assertion Processors. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi |
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi |
A New Approach for Design and Verification of Transaction Level Models. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari |
Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. |
AICCSA |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi |
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. |
DDECS |
2007 |
DBLP BibTeX RDF |
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| 1 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari |
Assertion based design error diagnosis for core-based SoCs. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Hassan Ghasemzadeh, Sepideh Sepideh Mazrouee, Mohammad Reza Kakoee |
Modified Pseudo LRU Replacement Algorithm. |
ECBS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Bijan Alizadeh, Mohammad Reza Kakoee |
Using Integer Equations for High Level Formal Verification Property Checking. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
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