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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 14 publication records. Showing 14 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Aminul Islam, Mohd. Hasan |
A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell.  |
Microelectronics Reliability  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | S. D. Pable, Mohd. Hasan |
Ultra-low-power signaling challenges for subthreshold global interconnects.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | S. D. Pable, Mohd. Hasan |
High speed interconnect through device optimization for subthreshold FPGA.  |
Microelectronics Journal  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | S. D. Pable, Mohd. Hasan |
Performance analysis of FPGA interconnect fabric for ultra-low power applications.  |
ICCCS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | S. D. Pable, Mohd. Hasan |
Performance optimization of CNFET for ultra-low power reconfigurable architecture.  |
ICCCS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Aminul Islam, Mohd. Hasan |
High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology.  |
ICT  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | A. K. Kureshi, Mohd. Hasan |
Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron.  |
Microelectronics Journal  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | A. K. Kureshi, Naushad Alam, Mohd. Hasan, Tughrul Arslan |
Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing.  |
ISCAS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Naushad Alam, A. K. Kureshi, Mohd. Hasan, Tughrul Arslan |
Carbon Nanotube Interconnects for Low-power High-speed Applications.  |
ISCAS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Mohd. Hasan, A. K. Kureshi, Tughrul Arslan |
Leakage Reduction in FPGA Routing Multiplexers.  |
ISCAS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Wei Han, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan |
The development of high performance FFT IP cores through hybrid low power algorithmic methodology.  |
ASP-DAC  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Wei Han, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan |
Low power commutator for pipelined FFT processors.  |
ISCAS  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Mohd. Hasan, Tughrul Arslan |
A triple port RAM based low power commutator architecture for a pipelined FFT processor.  |
ISCAS  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Mohd. Hasan, Tughrul Arslan |
A coefficient memory addressing scheme for VLSI implementation of FFT processors.  |
ISCAS  |
2002 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #14 of 14 (100 per page; Change: )
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