| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani |
Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only).  |
FPGA  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi |
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi |
Block-based quantum-logic synthesis. |
Quantum Information & Computation |
2011 |
DBLP BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh |
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Behzad Salami, Morteza Saheb Zamani, Ali Jahanian |
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani |
Evaluation of FPGA routing architectures under process variation. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani |
Quantum physical synthesis: Improving physical design by netlist modifications. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
A library-based synthesis methodology for reversible logic. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Early Buffer Planning with Congestion Control Using Buffer Requirement Map. |
Journal of Circuits, Systems, and Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian |
Reversible circuit synthesis using a cycle-based approach. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni |
Reduction of process variation effect on FPGAs using multiple configurations. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi |
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani |
Rule-based optimization of reversible circuits. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi |
Improving Latency of Quantum Circuits by Gate Exchanging. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Improved performance and yield with chip master planning design methodology. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
chip planning, highway on chip, interconnect planning |
| 1 | Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
A cycle-based synthesis algorithm for reversible logic. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani |
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan |
A tileable switch module architecture for homogeneous 3D FPGAs. |
3DIC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani |
A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Using metro-on-chip in physical design flow for congestion and routability improvement. |
Microelectronics Journal |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani |
An architecture framework for an adaptive extensible processor. |
The Journal of Supercomputing |
2008 |
DBLP DOI BibTeX RDF |
Reconfigurable functional unit, Profiling, Temporal partitioning, Custom instruction, Extensible processor, Similarity detection |
| 1 | Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei |
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
FPGA-Based Circuit Model Emulation of Quantum Algorithms. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani |
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi |
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani |
Performance Improvement of Physical Retiming with Shortcut Insertion. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Performance and Timing Yield Enhancement using Highway-on-Chip Planning. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi |
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi |
Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani |
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi |
An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami |
Design space exploration for a coarse grain accelerator. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arash Mehdizadeh, Morteza Saheb Zamani |
Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. |
AICCSA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami |
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian |
Evaluation, prediction and reduction of routing congestion. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi |
An Efficient Analytical Approach to Path-Based Buffer Insertion. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour |
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Improved timing closure by early buffer planning in floor-placement design flow. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer planning, design convergence, buffer insertion |
| 1 | Hamid Reza Kheirabadi, Morteza Saheb Zamani |
An efficient net ordering algorithm for buffer insertion. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer usage, net ordering, buffer insertion |
| 1 | Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami |
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
A novel synthesis algorithm for reversible circuits. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi |
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. |
Microprocessors and Microsystems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani |
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani |
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
Buffer planning, incremental placement, buffer insertion |
| 1 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori |
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. |
ERSA |
2006 |
DBLP BibTeX RDF |
|
| 1 | Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian |
Prediction and reduction of routing congestion. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
placement, physical design, congestion, routability |
| 1 | Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami |
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue |
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi |
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. |
EUC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi |
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour |
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. |
FPT |
2005 |
DBLP BibTeX RDF |
|
| 1 | Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei |
A novel reconfigurable hardware architecture for IP address lookup. |
ANCS |
2005 |
DBLP DOI BibTeX RDF |
field-programmable gate array (FPGA), application specific integrated circuit (ASIC), hashing, reconfigurable hardware, longest prefix matching, IP address lookup |
| 1 | Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi |
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. |
FCCM |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi |
Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. |
Evolvable Hardware |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Morteza Saheb Zamani, Graham R. Hellestrand |
A neural network approach to the placement problem. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Morteza Saheb Zamani, Graham R. Hellestrand |
A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Morteza Saheb Zamani, Graham R. Hellestrand |
A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. |
IWANN |
1995 |
DBLP DOI BibTeX RDF |
|
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