Search results for "Murali Jayapala"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	EMPIRE: Empirical power/area/timing models for register files.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala, Francky Catthoor	Locality optimization in a compiler for wireless applications.	Design Autom. for Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor	Playing the trade-off game: Architecture exploration using Coffeee.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest	Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris	Compilation Technique for Loop Overhead Minimization.	DSD	2009	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor	Address Generation Optimization for Embedded High-Performance Processors: A Survey.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	optimization, embedded, address generation
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation shuffling over cycle boundaries for low energy L0 clustering.	ASAP	2008	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
1	Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest	Coffee: COmpiler Framework for Energy-Aware Exploration.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
1	Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest	Semi Custom Design: A Case Study on SIMD Shufflers.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.	ARCS	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal	Very wide register: an asymmetric register file organization for low power embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
1	Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor	Locality optimization in wireless applications.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	access, reuse, layout, spatial, temporal, loop-nest
1	Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck	Instruction Transfer And Storage Exploration for Low Energy VLIWs.	SiPS	2006	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor	Instruction buffering exploration for low energy embedded processors.	J. Embedded Computing	2005	DBLP BibTeX RDF
1	Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck	Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design
1	Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina	Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.	ASAP	2005	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.	ESTImedia	2005	DBLP DOI BibTeX RDF
1	Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck	L0 Cluster Synthesis and Operation Shuffling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal	L0 buffer energy optimization through scheduling and exploration.	SAC	2004	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal	Instruction buffering exploration for low energy VLIWs with instruction clusters.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll	Design Style Case Study for Embedded Multi Media Compute Nodes.	RTSS	2004	DBLP DOI BibTeX RDF
1	Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal	Low Power Coarse-Grained Reconfigurable Instruction Set Processor.	FPL	2003	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor	Instruction Buffering Exploration for Low Energy Embedded Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck	Matador: An Exploration Environment for System-Design.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal	A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.	VLSI Design	2002	DBLP DOI BibTeX RDF	coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
1	Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins	CRISP: A Template for Reconfigurable Instruction Set Processors.	FPL	2001	DBLP DOI BibTeX RDF

Publications of "Murali Jayapala" ( http://dblp.L3S.de/Authors/Murali_Jayapala )