Search results for "N. P. van der Meijs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Amir Zjajo, Nick van der Meijs, Rene van Leuken	Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method.	ISQED	2012	DBLP DOI BibTeX RDF
1	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Crosstalk-aware statistical interconnect delay calculation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Transistor-level gate model based statistical timing analysis considering correlations.	DATE	2012	DBLP BibTeX RDF
1	Pieter Harpe, Cui Zhou, Yu Bi, N. P. van der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke de Groot	A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Yu Bi, Pieter Harpe, N. P. van der Meijs	Efficient sensitivity-based capacitance modeling for systematic and random geometric variations.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs	Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yu Bi, Simon de Graaf, Nick van der Meijs	Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique.	CICC	2011	DBLP DOI BibTeX RDF
1	Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luis Miguel Silveira, Nick van der Meijs	Fast statistical analysis of RC nets subject to manufacturing variabilities.	DATE	2011	DBLP BibTeX RDF
1	Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Pseudo circuit model for representing uncertainty in waveforms.	DATE	2011	DBLP BibTeX RDF
1	Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Statistical Moment Estimation of Delay and Power in Circuit Simulation.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs	Noise analysis of non-linear dynamic integrated circuits.	CICC	2010	DBLP DOI BibTeX RDF
1	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
1	Alejandro Viteri, Amir Zjajo, Thijmen Hamoen, Nick van der Meijs	Digital cartesian feedback linearization of switched mode power amplifiers.	ICECS	2010	DBLP DOI BibTeX RDF
1	Yu Bi, Kees-Jan van der Kolk, Nick van der Meijs	Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors.	CICC	2009	DBLP DOI BibTeX RDF
1	Nuo Li, Nick van der Meijs	A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system.	SoCC	2009	DBLP DOI BibTeX RDF
1	Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten	Statistically Aware Buffer Planning.	DATE	2004	DBLP DOI BibTeX RDF
1	Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten	Simultaneous Analytic Area and Power Optimization for Repeater Insertion.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Eelco Schrik, N. P. van der Meijs	Combined BEM/FEM substrate resistance modeling.	DAC	2002	DBLP DOI BibTeX RDF	modeling, finite element method, boundary element method, substrate noise
1	Eelco Schrik, Patrick Dewilde, N. P. van der Meijs	Theoretical and practical validation of combined BEM/FEM substrate resistance modeling.	ICCAD	2002	DBLP DOI BibTeX RDF
1	A. J. Dammers, N. P. van der Meijs	Virtual screening: a step towards a sparse partial inductance matrix.	ICCAD	1999	DBLP BibTeX RDF
1	U. Geigenmüller, N. P. van der Meijs	Cartesian multipole based numerical integration for 3D capacitance extraction.	ED&TC	1997	DBLP DOI BibTeX RDF
1	P. J. H. Elias, N. P. van der Meijs	Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency.	DAC	1996	DBLP DOI BibTeX RDF
1	Arjan J. van Genderen, N. P. van der Meijs	Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction.	DAC	1996	DBLP DOI BibTeX RDF
1	N. P. van der Meijs, T. Smedes	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
1	N. P. van der Meijs, Arjan J. van Genderen	Delayed Frontal Solution for Finite-Element Based Resistance Extraction.	DAC	1995	DBLP DOI BibTeX RDF
1	T. Smedes, N. P. van der Meijs, Arjan J. van Genderen	Extraction of circuit models for substrate cross-talk.	ICCAD	1995	DBLP DOI BibTeX RDF	Substrate Cross-talk, Layout Verification, Boundary Element Method, Green's Function
1	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
1	Arjan J. van Genderen, N. P. van der Meijs	Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures.	ICCAD	1993	DBLP DOI BibTeX RDF
1	N. P. van der Meijs, Arjan J. van Genderen	An Efficient Finite Element Method for Submicron IC Capacitance Extraction.	DAC	1989	DBLP DOI BibTeX RDF

Publications of N. P. van der Meijs Nick van der Meijs ( http://dblp.L3S.de/Authors/N._P._van_der_Meijs )