Search results for "N. Pete Sedcole"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung	Fault tolerance and reliability in field-programmable gate arrays.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Wave-pipelined intra-chip signaling for on-FPGA communications.	Integration	2010	DBLP DOI BibTeX RDF
1	Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
1	Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Self-Measurement of Combinatorial Circuit Delays in FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	FPGA, Testing, configuration, delay measurement
1	N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung	Compensating for variability in FPGAs by re-mapping and re-placement.	FPL	2009	DBLP DOI BibTeX RDF
1	Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung	Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.	ISCAS	2009	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	TRETS	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
1	Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung	Fault tolerant methods for reliability in FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
1	Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole	Combating process variation on FPGAS with a precise at-speed delay measurement method.	FPL	2008	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung	Characterisation of FPGA Clock Variability.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Implementation of Wave-Pipelined Interconnects in FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Interconnection lengths and delays estimation for communication links in FPGAs.	SLIP	2008	DBLP DOI BibTeX RDF	communciation link, interconnection length prediction, FPGA
1	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Global interconnections in FPGAs: modeling and performance analysis.	SLIP	2008	DBLP DOI BibTeX RDF	FPGA, throughput, interconnection, wave-pipelined
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung	Measuring and modeling FPGA clock variability.	FPGA	2008	DBLP DOI BibTeX RDF	within-die variability, modeling, FPGA, process variation, clock skew
1	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	Run-Time Integration of Reconfigurable Video Processing Systems.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.	NOCS	2007	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
1	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	On-Chip Communication in Run-Time Assembled Reconfigurable Systems.	ICSAMOS	2006	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	On-FPGA Communication Architectures and Design Factors.	FPL	2006	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght	Modular Partial Reconfiguration in Virtex FPGAs.	FPL	2005	DBLP BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	A Structured Methodology for System-on-an-FPGA Design.	FPL	2004	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	A Structured System Methodology for FPGA Based System-on-A-Chip Design.	FCCM	2004	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	A Reconfigurable Platform for Real-Time Embedded Video Image Processing.	FPL	2003	DBLP DOI BibTeX RDF

Publications of "N. Pete Sedcole" ( http://dblp.L3S.de/Authors/N._Pete_Sedcole )