| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
Mach-Zehnder interferometer based design of all optical reversible binary adder. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan |
Run-time power-gating in caches of GPUs for leakage energy savings. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Koustav Bhattacharya, N. Ranganathan |
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yue Wang, N. Ranganathan |
An Instruction-Level Energy Estimation and Optimization Methodology for GPU. |
CIT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, N. Ranganathan |
A new reversible design of BCD adder. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
CGMT, FGMT, Niagara, in-order, SMT, M5 |
| 1 | Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan |
Redundancy Mining for Soft Error Detection in Multicore Processors. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
fault tolerance, Soft errors, multicore processors |
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits |
CoRR |
2011 |
DBLP BibTeX RDF |
|
| 1 | Upavan Gupta, Nagarajan Ranganathan |
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Morrison, Nagarajan Ranganathan |
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkataraman Mahalingam, N. Ranganathan |
Timing-Based Placement Considering Uncertainty Due to Process Variations. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt |
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Upavan Gupta, Nagarajan Ranganathan |
A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. |
IEEE Trans. Knowl. Data Eng. |
2010 |
DBLP DOI BibTeX RDF |
Equipartitioning, clustering, game theory, Nash equilibrium, compaction |
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Quantum Cost, Delay, Sequential Circuits, Reversible Logic |
| 1 | Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan |
A Strategy for Soft Error Reduction in Multi Core Designs. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam |
Variation-aware multimetric optimization during gate sizing. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise |
| 1 | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
A Framework for Power-Gating Functional Units in Embedded Microprocessors. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim |
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
Exploring Compiler Optimizations for Enhancing Power Gating. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan |
A VLSI System Architecture for Optical Flow Computation. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, Nagarajan Ranganathan |
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
Compiler-directed leakage reduction in embedded microprocessors. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow |
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam |
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
optimization, delay, power, gate sizing, crosstalk noise, fuzzy programming |
| 1 | Venkataraman Mahalingam, Nagarajan Ranganathan |
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Upavan Gupta, Nagarajan Ranganathan |
An expected-utility based approach to variation aware VLSI optimization under scarce information. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A linear programming formulation for security-aware gate sizing. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing |
| 1 | Upavan Gupta, Nagarajan Ranganathan |
A microeconomic approach to multi-objective spatial clustering. |
ICPR |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkataraman Mahalingam, N. Ranganathan |
Variation Aware Timing Based Placement Using Fuzzy Programming. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan |
A Sequential Distinguisher for Covert Channel Identification. |
I. J. Network Security |
2007 |
DBLP BibTeX RDF |
|
| 1 | Upavan Gupta, Nagarajan Ranganathan |
Multievent Crisis Management Using Noncooperative Multistep Games. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
game theory, Nash equilibrium, Emergency response, homeland security |
| 1 | Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan |
VLSI architecture and chip for combined invisible robust and fragile watermarking. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
Integrated Gate and Wire Sizing at Post Layout Level. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Upavan Gupta, Nagarajan Ranganathan |
A microeconomic approach to multi-robot team formation. |
IROS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan |
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan |
Improving the reliability of on-chip L2 cache using redundancy. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
ILP models for simultaneous energy and transient power minimization during behavioral synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power |
| 1 | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan |
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
sequential circuits, Dynamic Bayesian networks, TDM |
| 1 | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
A novel approach for variation aware power minimization during gate sizing. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkataraman Mahalingam, N. Ranganathan |
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay |
| 1 | Narender Hanchate, Nagarajan Ranganathan |
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay |
| 1 | Venkataraman Mahalingam, Nagarajan Ranganathan |
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
interpolation, Computer arithmetic, error analysis, logarithmic number system |
| 1 | Narender Hanchate, Nagarajan Ranganathan |
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate |
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswath Oruganti, Nagarajan Ranganathan |
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh |
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan |
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling |
| 1 | Venkataraman Mahalingam, N. Ranganathan |
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan |
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan |
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa |
A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa |
A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ranganathan |
Editorial. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Sanjukta Bhanja, N. Ranganathan |
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan |
Stochastic channel-adaptive rate control for wireless video transmission. |
Pattern Recognition Letters |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
LECTOR: a technique for leakage reduction in CMOS circuits. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Nagarajan Ranganathan |
A framework for energy and transient power reduction during behavioral synthesis. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui |
Control and Data Flow Graph Extraction for High-Level Synthesis. (PDF / PS) |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa |
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi |
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Narender Hanchate, Nagarajan Ranganathan |
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjukta Bhanja, N. Ranganathan |
Switching activity estimation of VLSI circuits using Bayesian networks. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdel Ejnioui, N. Ranganathan |
Routing on field-programmable switch matrices. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
Petri net modeling of gate and interconnect delays for power estimation. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdel Ejnioui, N. Ranganathan |
Multiterminal net routing for partial crossbar-based multi-FPGA systems. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
A game theoretic approach for power optimization during behavioral synthesis. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
Peak Power Minimization Through Datapath Scheduling. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
Simultaneous peak and average power minimization during datapath scheduling for DSP processors. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages |
| 1 | Saraju P. Mohanty, N. Ranganathan |
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
A Game-Theoretic Approach for Binding in Behavioral Synthesis. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan |
Energy Efficient Scheduling for Datapath Synthesis. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ranganathan, Ashok K. Murugavel |
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ranganathan, Ashok K. Murugavel |
A low power scheduler using game theory. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
game theory, high-level synthesis, low power design, auction theory |
| 1 | Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali |
Least-square estimation of average power in digital CMOS circuits. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna |
Datapath Scheduling using Dynamic Frequency Clocking. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
Petri net modeling of gate and interconnect delays for power estimation. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Sitaraman, N. Ranganathan, Abdel Ejnioui |
A VLSI Architecture for Object Recognition Using Tree Matching. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok K. Murugavel, N. Ranganathan |
A Real Delay Switching Activity Simulator Based on Petri Net Modeling. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjukta Bhanja, N. Ranganathan |
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjukta Bhanja, N. Ranganathan |
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ranganathan, Minesh I. Patel, R. Sathyamurthy |
An intelligent system for failure detection and control in an autonomous underwater vehicle. |
IEEE Transactions on Systems, Man, and Cybernetics, Part A |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdel Ejnioui, N. Ranganathan |
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan |
Context-based lossless image coding using EZW framework. |
IEEE Trans. Circuits Syst. Video Techn. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjukta Bhanja, N. Ranganathan |
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
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