|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 30 occurrences of 20 keywords
|
|
|
|
|
Results
Found 42 publication records. Showing 42 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jungseob Lee, Nam Sung Kim |
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek A. Sinkar, Hao Wang, Nam Sung Kim |
Workload-aware voltage regulator optimization for power efficient multi-core processors. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Jacob Adriaens, Katherine Compton, Nam Sung Kim, Michael J. Schulte |
The case for GPGPU spatial multitasking. |
HPCA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel W. Chang, Nam Sung Kim, Michael J. Schulte |
Analyzing the performance and energy impact of 3D memory integration on embedded DSPs. |
ICSAMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja |
A low cost approach to calibrate on-chip thermal sensors. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Paritosh Pratap Ajgaonkar, Nam Sung Kim |
Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation. |
ISPASS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Vijay Sathisha, Michael J. Schulte, Katherine Compton, Nam Sung Kim |
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling. |
PACT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte |
Energy-efficient floating-point arithmetic for software-defined radio architectures. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek A. Sinkar, Nam Sung Kim |
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte |
Scratchpad memory optimizations for digital signal processing applications. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David J. Palframan, Nam Sung Kim, Mikko H. Lipasti |
Time redundant parity for low-cost transient error detection. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim |
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors. |
HPCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongkeun Oh, Charlie Chung-Ping Chen, Nam Sung Kim, Yu Hen Hu |
The compatibility analysis of thread migration and DVFS in multi-core processor. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek A. Sinkar, Nam Sung Kim |
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim |
Workload-adaptive process tuning strategy for power-efficient multi-core processors. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
process parameter tuning, DVFS, multi-core processor |
| 1 | Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti |
Combating Aging with the Colt Duty Cycle Equalizer. |
MICRO |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Shi-Ting Zhou, Nam Sung Kim |
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu |
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim |
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim |
Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek A. Sinkar, Nam Sung Kim |
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
adaptive voltage positioning, multicore processor |
| 1 | Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin |
Frequency and yield optimization using power gates in power-constrained designs. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
optimization, yield, power gate, frequency |
| 1 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
| 1 | Jungseob Lee, Nam Sung Kim |
Optimizing total power of many-core processors considering voltage scaling limit and process variations. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
voltage and frequency scaling, process variations, parallel applications, many-core processor |
| 1 | Jungseob Lee, Nam Sung Kim |
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
multicore processor, DVFS, power gating |
| 1 | David Roberts, Nam Sung Kim, Trevor N. Mudge |
On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge |
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | David Roberts, Nam Sung Kim, Trevor N. Mudge |
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim |
Yield-driven near-threshold SRAM design. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, David Blaauw, Trevor N. Mudge |
Quantitative analysis and optimization techniques for on-chip cache leakage power. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge |
Total leakage optimization strategies for multi-level caches. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
low power, cache memory, gate leakage |
| 1 | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge |
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner |
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge |
Circuit and microarchitectural techniques for reducing cache leakage power. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge |
Microarchitectural power modeling techniques for deep sub-micron microprocessors. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
power modeling, deep sub-micron |
| 1 | Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan |
Leakage Current: Moore's Law Meets Static Power. |
IEEE Computer |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, Trevor N. Mudge |
The microarchitecture of a low power register file. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
| 1 | Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge |
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, Trevor N. Mudge |
Reducing register ports using delayed write-back queues and operand pre-fetch. |
ICS |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
| 1 | Nam Sung Kim, David Blaauw, Trevor N. Mudge |
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge |
Drowsy Caches: Simple Techniques for Reducing Leakage Power. (PDF / PS) |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge |
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #42 of 42 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")