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Publications of "Narendra Devta-Prasanna" ( http://dblp.L3S.de/Authors/Narendra_Devta-Prasanna )

  Author page on DBLP  Author page in RDF  Community of Narendra Devta-Prasanna in ASPL-2

Publication years (Num. hits)
2005-2009 (18) 2010 (2)
Publication types (Num. hits)
article(2) inproceedings(18)
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Found 20 publication records. Showing 20 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz Multiple fault activation cycle tests for transistor stuck-open faults. Search on Bibsonomy ITC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Arun Gunda Clock Gate Test Points. Search on Bibsonomy ITC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy Accurate measurement of small delay defect coverage of test patterns. Search on Bibsonomy ITC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. Search on Bibsonomy ITC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Detectability of internal bridging faults in scan chains. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia Effective and Efficient Test Pattern Generation for Small Delay Defect. Search on Bibsonomy VTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Improving the Detectability of Resistive Open Faults in Scan Cells. Search on Bibsonomy DFT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda Comparative study of centralised and distributed compatibility-based test data compression. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Detection of Internal Stuck-open Faults in Scan Chains. Search on Bibsonomy ITC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Faults in scan cells, stuck-at and stuck-on faults
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz An Enhanced Logic BIST Architecture for Online Testing. Search on Bibsonomy IOLTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda Systematic Scan Reconfiguration. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
1Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz Test Generation for Open Defects in CMOS Circuits. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz Methods for improving transition delay fault coverage using broadside tests. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda Should Illinois-Scan Based Architectures be Centralized or Distributed? Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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