| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Eric P. Kim, Naresh R. Shanbhag |
Soft N-Modular Redundancy.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag |
VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. |
IEEE Transactions on Information Theory |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag |
Least squares approximation and polyphase decomposition for pipelining recursive filters. |
ICASSP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric P. Kim, Naresh R. Shanbhag |
An energy-efficient multiple-input multiple-output (MIMO) detector architecture. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein |
System energy minimization via joint optimization of the DC-DC converter and the core. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag |
Low power and error resilient PN code acquisition filter via statistical error compensation. |
CICC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag |
Timing error statistics for energy-efficient robust DSP systems. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, Andrew C. Singer |
System-assisted analog mixed-signal design. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag |
Computation as estimation: a general framework for robustness and energy efficiency in SoCs. |
IEEE Transactions on Signal Processing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Naresh R. Shanbhag |
Minimum-Energy Operation Via Error Resiliency. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones |
Stochastic Networked Computation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajan Narasimha, Naresh R. Shanbhag |
Design of Energy-Efficient High-Speed Links via Forward Error Correction. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric P. Kim, Naresh R. Shanbhag |
Soft NMR: Analysis & application to DSP systems. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim (eds.) |
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 |
ISLPED |
2010 |
DBLP BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones |
Stochastic computation. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
algorithmic noise-tolerance, soft processing, stochastic computation, reliability, energy-efficiency, error-resiliency |
| 1 | Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne |
Energy-efficient high-speed interfaces. |
ISSCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto |
Transceiver circuits for optical communications. |
ISSCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer |
BER-optimal analog-to-digital converters for communication links. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Naresh R. Shanbhag |
Robust and energy-efficient DSP systems via output probability processing. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Naresh R. Shanbhag |
Error-resilient low-power Viterbi decoder architectures. |
IEEE Transactions on Signal Processing |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Junho Cho, Naresh R. Shanbhag, Wonyong Sung |
Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. |
SiPS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag |
Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. |
SiPS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag |
Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. |
GLOBECOM |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Varatkar, Naresh R. Shanbhag |
Error-Resilient Motion Estimation Architecture. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag |
Joint Equalization and Coding for On-Chip Bus Communication. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey |
The Search for Alternative Computational Paradigms. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shrikanth Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag |
Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Naresh R. Shanbhag |
Error-resilient low-power Viterbi decoders via state clustering. |
SiPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami A. Abdallah, Naresh R. Shanbhag |
Error-resilient low-power Viterbi decoders. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones |
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
reliable design, sensor network-on-chip, robust design |
| 1 | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones |
Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Varatkar, Naresh R. Shanbhag |
Variation-Tolerant Motion Estimation Architecture. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Zhang, Naresh R. Shanbhag |
Soft-Error-Rate-Analysis (SERA) Methodology. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Byonghyo Shim, Naresh R. Shanbhag |
Energy-efficient soft error-tolerant digital signal processing. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel |
Sequential Element Design With Built-In Soft Error Resilience. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Girish Varatkar, Naresh R. Shanbhag |
Energy-efficient motion estimation using error-tolerance. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
low-power, noise-tolerance |
| 1 | Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag |
Linear turbo equalization analysis via BER transfer and EXIT charts. |
IEEE Transactions on Signal Processing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
Coding for system-on-chip networks: a unified framework. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
Area-efficient high-throughput MAP decoder architectures. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. |
VLSI Signal Processing |
2005 |
DBLP DOI BibTeX RDF |
turbo-decoding message-passing algorithm, VLSI decoder architectures, LDPC codes, Ramanujan graphs |
| 1 | Naresh R. Shanbhag, Keshab K. Parhi |
Guest Editorial. |
VLSI Signal Processing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
Energy Efficient VLSI Architecture for Linear Turbo Equalizer. |
VLSI Signal Processing |
2005 |
DBLP DOI BibTeX RDF |
iterative equalizer, SISO, turbo, architecture, low-power, iterative decoder |
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan |
Joint Equalization and Coding for On-Chip Bus Communication. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
A low-power bus design using joint repeater insertion and coding. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
low-power, coding, crosstalk, repeaters |
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Zhang, Naresh R. Shanbhag |
An energy-efficient circuit technique for single event transient noise-tolerance. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag |
Reliable and Efficient System-on-Chip Design. |
IEEE Computer |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag |
Reliable low-power digital signal processing via reduced precision redundancy. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
Coding for system-on-chip networks: a unified framework. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
bus coding, crosstalk avoidance, low-power, error-correcting codes, low-swing |
| 1 | Naresh R. Shanbhag |
A communication-theoretic design paradigm for reliable SOCs. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
reliability, communications, low-power, coding, system-on-a-chip |
| 1 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
Switching methods for linear turbo equalization. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Zhang, Naresh R. Shanbhag |
A soft error rate analysis (SERA) methodology. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag |
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang 0003, Naresh R. Shanbhag |
Low-power filtering via adaptive error-cancellation. |
IEEE Transactions on Signal Processing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Byonghyo Shim, Naresh R. Shanbhag |
Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. |
IEEE Transactions on Signal Processing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang 0003, Naresh R. Shanbhag |
Low-power MIMO signal processing. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
VLSI architectures for SISO-APP decoders. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang 0003, Naresh R. Shanbhag |
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
High-throughput LDPC decoders. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
A low-power VLSI architecture for turbo decoding. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
MAP decoder, low power architecture, turbo decoding |
| 1 | Hyeon-Min Bae, Naresh R. Shanbhag |
High bandwidth transimpedance amplifier design using active transmission lines. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
Architecture-aware low-density parity-check codes. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Byonghyo Shim, Naresh R. Shanbhag |
Performance analysis of algorithmic noise-tolerance techniques. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Balamurugan, Naresh R. Shanbhag |
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
Low-power VLSI decoder architectures for LDPC codes. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
BCJR algorithm, lower power architectures, LDPC codes |
| 1 | Naresh R. Shanbhag |
Reliable and energy-efficient digital signal processing. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
reliability, communications, low-power, energy-efficiency, noise, broadband, noise-tolerance, deep submicron |
| 1 | Mohammad M. Mansour, Naresh R. Shanbhag |
Simplified current and delay models for deep submicron CMOS digital circuits. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Dilip V. Sarwate, Naresh R. Shanbhag |
High-speed architectures for Reed-Solomon decoders. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamohana Hegde, Naresh R. Shanbhag |
Soft digital signal processing. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Wayne Burleson, Naresh R. Shanbhag |
Guest Editorial: Reconfigurable Signal Processing Systems. |
VLSI Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran |
Total System Energy Minimization for Wireless Image Transmission. |
VLSI Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
indoor wireless transmission, low power, energy minimization, joint source-channel coding |
| 1 | Lei Wang 0003, Naresh R. Shanbhag |
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
Ethernet |
| 1 | Rajamohana Hegde, Naresh R. Shanbhag |
Toward achieving energy efficiency in presence of deep submicron noise. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, K. Soumyanath, Samuel Martin |
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
A coding framework for low-power address and data busses. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Information-theoretic bounds on average signal transition activity [VLSI systems]. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Goel, Naresh R. Shanbhag |
Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Balamurugan, Naresh R. Shanbhag |
Energy-efficient dynamic circuit design in the presence of crosstalk noise. |
ISLPED |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamohana Hegde, Naresh R. Shanbhag |
Energy-efficient signal processing via algorithmic noise-tolerance. |
ISLPED |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag |
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Low-power distributed arithmetic architectures using nonuniform memory partitioning. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang 0003, Naresh R. Shanbhag |
Noise-tolerant dynamic circuit design. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamohana Hegde, Naresh R. Shanbhag |
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag |
Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design. |
IJWIN |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Goel, Naresh R. Shanbhag |
Finite-precision analysis of the pipelined strength-reduced adaptive filter. |
IEEE Transactions on Signal Processing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, Gi-Hong Im |
VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access. |
IEEE Transactions on Signal Processing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Gi-Hong Im, Naresh R. Shanbhag |
A pipelined adaptive NEXT canceller. |
IEEE Transactions on Signal Processing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Decorrelating (DECOR) transformations for low-power adaptive filters. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | Rajamohana Hegde, Naresh R. Shanbhag |
Energy-efficiency in presence of deep submicron noise. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag, Manish Goel |
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN. |
IEEE Transactions on Signal Processing |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Analytical estimation of signal transition activity from word-level statistics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Goel, Naresh R. Shanbhag |
Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. |
ISLPED |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Analytical Estimation of Transition Activity From Word-Level Signal Statistics. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Achievable bounds on signal transition activity. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
achievable bounds, busses, Low power, information theory, power estimation, CMOS circuits, switching activity |
| 1 | Naresh R. Shanbhag, Gi-Hong Im |
Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations. |
IEEE Transactions on Signal Processing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Goel, Naresh R. Shanbhag |
Low-power adaptive filter architectures via strength reduction. |
ISLPED |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh R. Shanbhag |
Lower bounds on power dissipation for DSP algorithms. |
ISLPED |
1996 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")