Search results for "Ney Calazans"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans	Impact of C-elements in asynchronous circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Ney Calazans, Pascal Vivet	An accurate Single Event Effect digital design flow for reliable system level design.	DATE	2012	DBLP BibTeX RDF
1	Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose	A preliminary study on system-level impact of persistent main memory.	ISQED	2012	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin	CAFES: A framework for intrachip application modeling and communication architecture design.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans	Adapting a C-element design flow for low power.	ICECS	2011	DBLP DOI BibTeX RDF
1	Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans	A 65nm standard cell set and flow dedicated to automated asynchronous circuits design.	SoCC	2011	DBLP DOI BibTeX RDF
1	Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres	A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA
1	Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Arbitration and routing impact on NoC design.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans	Hermes-A - An Asynchronous NoC Router with Distributed Routing.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes	Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans	Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.	SoCC	2010	DBLP DOI BibTeX RDF
1	Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Dynamic Task Mapping for MPSoCs.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres	A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans	Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.	DATE	2009	DBLP BibTeX RDF
1	Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes	HeMPS - a Framework for NoC-based MPSoC Generation.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.	ReConFig	2009	DBLP DOI BibTeX RDF	floating point hardware, GALS design, FPGA, prototyping, embedded processor
1	Guilherme Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes	A 10 Gbps OTN Framer Implementation Targeting FPGA Devices.	ReConFig	2009	DBLP DOI BibTeX RDF	OTN, Optical Transport Network, Telecommunication Circuits, Framer, FPGA
1	Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes	NoC Power Estimation at the RTL Abstraction Level.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans	Triple Rail Logic Robustness against DPA.	ReConFig	2008	DBLP DOI BibTeX RDF	STTL, DPA, SCA, CPA
1	César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Comparison of network-on-chip mapping algorithms targeting low energy consumption.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans	Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya	Integrating Abstract NoC Models within MPSoC Design.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans	MOTIM: an industrial application using nocs.	SBCCI	2008	DBLP DOI BibTeX RDF	ethernet switch, FPGA, prototyping, networks on chip
1	Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert	Evaluating the robustness of secure triple track logic through prototyping.	SBCCI	2008	DBLP DOI BibTeX RDF	logic style, FPGA, side-channel attacks, DPA, DES, CPA
1	Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip	CoRR	2007	DBLP BibTeX RDF
1	Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes	SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Calazans, Fernando Moraes	Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Fernando Moraes, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
1	Everton Carara, Fernando Moraes, Ney Calazans	Router architecture for high-performance NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	session layer, switching modes, networks on chip, virtual channels
1	Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans	SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.	ICCD	2007	DBLP DOI BibTeX RDF
1	Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes	A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.	ReCoSoC	2007	DBLP BibTeX RDF
1	César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique	CoRR	2007	DBLP BibTeX RDF
1	Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes	MOTIM - A Scalable Architecture for Ethernet Switches.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Aline Mello, Ney Laert Vilar Calazans	Rate-based scheduling policy for QoS flows in networks on chip.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Evaluation of Algorithms for Low Energy Mapping onto NoCs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes	Reconfigurable Systems Enabled by a Network-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
1	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
1	Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes	Application driven traffic modeling for NoCs.	SBCCI	2006	DBLP DOI BibTeX RDF	QoS, applications, networks on chip, traffic modeling
1	Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes	Traffic generation and performance evaluation for mesh-based NoCs.	SBCCI	2005	DBLP DOI BibTeX RDF	performance evaluation, networks on chip, traffic modeling
1	Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes	Virtual channels in networks on chip: implementation and evaluation on hermes NoC.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, network-on-chip, virtual channel
1	Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans	MAIA: a framework for networks on chip generation and verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans	Models for Embedded Application Mapping onto NoCs: Timing Analysis.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin	Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.	SBCCI	2005	DBLP DOI BibTeX RDF	traffic effect, networks-on-chip, energy estimation, application mapping
1	César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis	Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.	DATE	2005	DBLP DOI BibTeX RDF
1	Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans	Energy and latency evaluation of NoC topologies.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost	HERMES: an infrastructure for low area overhead packet-switching networks on chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes	PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.	SBCCI	2004	DBLP DOI BibTeX RDF	dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration
1	Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
1	Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato	FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.	FPL	2004	DBLP DOI BibTeX RDF
1	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
1	Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans	A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans	Remote and Partial Reconfiguration of FPGAs: Tools and Trends.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans	Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.	DATE	2003	DBLP DOI BibTeX RDF
1	Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli	Projeto para Prototipação de um IP Soft Core MAC Ethernet.	RITA	2001	DBLP BibTeX RDF
1	Ney Laert Vilar Calazans	Boolean constrained encoding: a new formulation and a case study.	ICCAD	1994	DBLP DOI BibTeX RDF

Publications of Ney Calazans Ney Laert Vilar Calazans ( http://dblp.L3S.de/Authors/Ney_Calazans )