| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta |
VaMV: Variability-aware Memory Virtualization.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yi Wang, Luis Angel D. Bathen, Zili Shao, Nikil D. Dutt |
3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Grit Denker, Nikil Dutt, Sharad Mehrotra, Mark-Oliver Stehr, Carolyn L. Talcott, Nalini Venkatasubramanian |
Resilient dependable cyber-physical systems: a middleware perspective. |
J. Internet Services and Applications |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil Dutt, Mani B. Srivastava, Rajesh Gupta, Subhashish Mitra |
Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Kiyoung Choi, Nikil D. Dutt |
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt |
A Multi-Granularity Power Modeling Methodology for Embedded Processors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Leon Stok, Nikil D. Dutt, Soha Hassoun (eds.) |
Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 |
DAC |
2011 |
DBLP BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Nikil D. Dutt |
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Nikil D. Dutt, Dongyoun Shin, Sung-Soo Lim |
SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt |
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation. |
CASES |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil Dutt |
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian |
A Formal Methodology for Compositional Cross-Layer Optimization. |
Formal Modeling: Actors, Open Systems, Biological Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeffrey L. Krichmar, Nikil Dutt, Jayram Moorkanikara Nageswaran, Micah Richert |
Neuromorphic modeling abstractions and simulation of large-scale cortical networks. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt |
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt |
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar |
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Nikil D. Dutt |
PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors. |
WESS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt |
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian |
Partitioning techniques for partially protected caches in resource-constrained embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt |
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. |
TRETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi |
E < MC2: less energy through multi-copy cache. |
CASES |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt |
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power |
| 1 | Kazuyuki Tanimura, Nikil Dutt |
ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity. |
HOST |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt |
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. |
HiPEAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt |
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. |
ACM Trans. Embedded Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation |
| 1 | Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi |
System-level PVT variation-aware power exploration of on-chip communication architectures. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems |
| 1 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum |
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. |
Neural Networks |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek |
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt |
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt |
Fast Configurable-Cache Tuning With a Unified Second-Level Cache. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian |
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück |
Computing Spike-based Convolutions on GPUs. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück |
Live Demonstration: Computing Spike-based Convolutions on GPUs. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha |
A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations. |
MTV |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha |
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. |
ESTImedia |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Andrew Felch, Ashok Chandrasekhar, Nikil Dutt, Richard Granger, Alex Nicolau, Alexander V. Veidenbaum |
Brain Derived Vision Algorithm on High Performance Architectures. |
International Journal of Parallel Programming |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil Dutt, Jürgen Teich |
CODES+ISSS 2007 guest editors' introduction. |
Design Autom. for Emb. Sys. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabor Madl, Sudeep Pasricha, Nikil Dutt, Sherif Abdelwahed |
Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs. |
IEEE Trans. Industrial Informatics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek |
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi |
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi |
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir |
TRAM: A tool for Temperature and Reliability Aware Memory Design. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Nikil Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum |
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. |
IJCNN |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabor Madl, Nikil Dutt, Sherif Abdelwahed |
A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil D. Dutt |
Editorial. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt |
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie |
Register File Power Reduction Using Bypass Sensitive Compiler. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
reliability, global routing, thermal |
| 1 | Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi |
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha |
A framework for memory-aware multimedia application mapping on chip-multiprocessors. |
ESTImedia |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Issenin, Nikil Dutt |
Using FORAY Models to Enable MPSoC Memory Optimizations. |
International Journal of Parallel Programming |
2008 |
DBLP DOI BibTeX RDF |
FORAY model, affine index expressions, Embedded systems, MPSoC, memory optimizations, scratch pad memory |
| 1 | Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane |
Fast exploration of bus-based communication architectures at the CCATB abstraction. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus |
| 1 | Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian |
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
cosynthesis, energy, Real-time scheduling, MPSoC |
| 1 | Nikil Dutt |
Editorial. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil Dutt |
Editorial. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Nikil Dutt |
Specification-driven directed test generation for validation of pipelined processors. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Model checking, test generation, functional validation |
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil Dutt |
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini |
ESL hand-off: fact or EDA fiction? |
DAC |
2008 |
DBLP DOI BibTeX RDF |
sign-off, specification, formalism, ESL, hand-off |
| 1 | Nikil Dutt |
Quo vadis, BTSoC (Billion Transistor SoC)? |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Nikil Dutt |
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt |
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt |
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif |
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian |
Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. |
DIPES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian |
Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems. |
DIPES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil Dutt |
Memory-aware NoC Exploration and Design. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian |
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amin Khajeh Djahromi, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi |
Cross-layer co-exploration of exploiting error resilience for video over wireless applications. |
ESTImedia |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian |
Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. |
ACM Multimedia |
2008 |
DBLP DOI BibTeX RDF |
error-awareness, cross-layer, soft error, video encoding |
| 1 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko |
Compiler driven data layout optimization for regular/irregular array access patterns. |
LCTES |
2008 |
DBLP DOI BibTeX RDF |
compiler, memory hierarchy, energy consumption, data placement |
| 1 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt |
Methodology for multi-granularity embedded processor power model generation for an ESL design flow. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
system-on-chip, embedded processor, power modeling, esl |
| 1 | Liang Cheng, Shivajit Mohapatra, Magda El Zarki, Nikil D. Dutt, Nalini Venkatasubramanian |
Quality-Based Backlight Optimization for Video Playback on Handheld Devices. |
Adv. in MM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
| 1 | Sudeep Pasricha, Nikil D. Dutt |
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne |
Introduction of Architecturally Visible Storage in Instruction Set Extensions. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek |
Automatic Design Space Exploration of Register Bypasses in Embedded Processors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil D. Dutt, Nalini Venkatasubramanian |
A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems. |
FMOODS |
2007 |
DBLP DOI BibTeX RDF |
Probabilistic Formal Methods, Resource Management, Statistical Analysis, Cross-layer Optimization |
| 1 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs |
| 1 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich (eds.) |
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 |
CODES+ISSS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Chulho Shin, Peter Grun, Nizar Romdhane, Christopher K. Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll |
Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications. |
Design Autom. for Emb. Sys. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt |
DRDU: A data reuse analysis technique for efficient scratch-pad memory management. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Scratch-pad memory management, data reuse analysis, memory hierarchy, compiler analysis |
| 1 | Nikil Dutt |
Editorial. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Reshadi, Nikil Dutt |
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Ilya Issenin, Nikil Dutt |
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne |
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Shivajit Mohapatra, Nikil Dutt, Alexandru Nicolau, Nalini Venkatasubramanian |
DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices. |
IEEE Journal on Selected Areas in Communications |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabor Madl, Nikil Dutt, Sherif Abdelwahed |
Performance estimation of distributed real-time embedded systems by discrete event simulations. |
EMSOFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Radu Cornea, Alex Nicolau, Nikil Dutt |
Annotation Integration and Trade-off Analysis for Multimedia Applications. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian |
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters. |
FORMATS |
2007 |
DBLP DOI BibTeX RDF |
Iterative System Tuning, Statistical Formal Methods, System Realization, Cross-layer Timing/QoS/resource Provisioning for Distributed Systems, Formal Modeling |
| 1 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera |
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek |
Software controlled memory layout reorganization for irregular array access patterns. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
energy consumption, data layout, scratch pad memory |
| 1 | Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha |
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Zhu, Aviral Shrivastava, Nikil Dutt |
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Issenin, Nikil Dutt |
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. |
IESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil Dutt |
Modeling of Software-Hardware Complexes. |
IESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger |
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. |
PARCO |
2007 |
DBLP BibTeX RDF |
|
| 1 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt |
System level power estimation methodology with H.264 decoder prediction IP case study. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers |
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