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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4 occurrences of 4 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy |
Significance driven computation on next-generation unreliable platforms.  |
DAC  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Muhsen Owaida, Nikolaos Bellas, Konstantis Daloukas, Christos D. Antonopoulos |
Synthesis of Platform Architectures from OpenCL Programs. |
FCCM |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos |
Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors. |
FCCM |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis, Konstantinos Krommydas, G. Tsoumblekas |
Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore Processors. |
FCCM |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Konstantinos Krommydas, Christos D. Antonopoulos, Nikolaos Bellas, Wu-chun Feng |
AVS video decoder on multicore systems: Optimizations and tradeoffs. |
ICME |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas |
GLOpenCL: OpenCL support on hardware- and software-managed cache multicores. |
HiPEAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis |
Massively parallel programming models used as hardware description languages: The OpenCL case. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sek M. Chai, Branislav Kisacanin, Nikolaos Bellas |
Special issue on embedded vision. |
Computer Vision and Image Understanding |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas, Sek M. Chai |
Fisheye lens distortion correction on multicore and hardware accelerator platforms. |
IPDPS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Konstantinos Krommydas, George Tsoublekas, Christos D. Antonopoulos, Nikolaos Bellas |
Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor. |
ICME |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier, Abelardo López-Lagunas |
Proteus: An architectural synthesis tool based on the stream programming paradigm. |
FPL |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators. |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas |
Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
cell b.e., heterogeneous multi-core processors, real-time, parallel programming, image warping, stencil computation |
| 1 | Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal |
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
Mapping streaming architectures on reconfigurable platforms. |
SIGARCH Computer Architecture News |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
An Architectural Framework for Automated Streaming Kernel Selection. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas |
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
Template-Based Generation of Streaming Accelators from a High Level Presentation. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas |
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Bellas, Arnold Yanof |
An Image Processing Pipeline with Digital Compensation of Low Cost Optics for Mobile Telephony. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Georgios I. Stamoulis, Maria G. Koziri, Ioannis Katsavounidis, Nikolaos Bellas |
A Low - Power VLSI Architecture for Intra Prediction in H.264. |
Panhellenic Conference on Informatics |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, G. Stamoulis |
Architectural and compiler techniques for energy reduction in high-performance microprocessors. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos |
Using dynamic cache management techniques to reduce energy in general purpose processors. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos |
Using dynamic cache management techniques to reduce energy in a high-performance processor. |
ISLPED |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos |
An analytical, transistor-level energy model for SRAM-based caches. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis |
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos |
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
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