| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chunxiao Li, Niraj K. Jha, Anand Raghunathan |
Secure reconfiguration of software-defined radio.  |
ACM Trans. Embedded Comput. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha |
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Shoaib, Niraj K. Jha, Naveen Verma |
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
A framework for defending embedded systems against software attacks. |
ACM Trans. Embedded Comput. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Meng Zhang, Niraj K. Jha |
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. |
JETC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay N. Bhoj, Niraj K. Jha |
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Shoaib, Niraj K. Jha, Naveen Verma |
A low-energy computation platform for data-driven biomedical monitoring algorithms. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Yi Lee, Niraj K. Jha |
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourindra Chaudhuri, Niraj K. Jha |
3D vs. 2D analysis of FinFET logic gates under process variations. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay N. Bhoj, Niraj K. Jha |
Gated-diode FinFET DRAMs: Device and circuit design-considerations. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Yi Lee, Niraj K. Jha |
FinFET-based power simulator for interconnection networks. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Niraj K. Jha |
Editorial: New Associate Editor Appointments. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha |
Die-level leakage power analysis of FinFET circuits considering process variations. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunxiao Li, Anand Raghunathan, Niraj K. Jha |
A Secure User Interface for Web Applications Running Under an Untrusted Operating System. |
CIT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Prateek Mishra, Niraj K. Jha |
Low-power FinFET circuit synthesis using surface orientation optimization. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chunxiao Li, Anand Raghunathan, Niraj K. Jha |
Secure Virtual Machine Execution under an Untrusted Management OS. |
IEEE CLOUD |
2010 |
DBLP DOI BibTeX RDF |
computing as a service, cloud computing, virtual machine, memory protection, trusted computing base |
| 1 | Prateek Mishra, Anish Muttreja, Niraj K. Jha |
Low-power FinFET circuit synthesis using multiple supply and threshold voltages. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
Low-power, linear programming, synthesis, TCMS |
| 1 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
A hybrid nano-CMOS architecture for defect and fault tolerance. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
nanotechnology, Defect tolerance, nanowires |
| 1 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
design optimization flow, logic folding, Dynamic reconfiguration, NATURE |
| 1 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Niraj K. Jha |
Editorial Appointments for the 2009-2010 Term. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty |
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muzaffer O. Simsir, Niraj K. Jha |
Thermal characterization of BIST, scan design and sequential test methodologies. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha |
GARNET: A detailed on-chip network model inside a full-system simulator. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha |
In-network coherence filtering: snoopy coherence without broadcasts. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunxiao Li, Anand Raghunathan, Niraj K. Jha |
An architecture for secure software defined radio. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha |
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay N. Bhoj, Niraj K. Jha |
Pragmatic design of gated-diode FinFET DRAMs. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Yi Lee, Niraj K. Jha |
FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
Analysis and design of a hardware/software trusted platform module for embedded systems. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, multiprocessor systems, Custom instructions |
| 1 | Yunsi Fei, Lin Zhong, Niraj K. Jha |
An energy-aware framework for dynamic software management in mobile computing systems. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
energy macromodel, runtime coordination, Software adaptation |
| 1 | Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha |
Toward Ideal On-Chip Communication Using Express Virtual Channels. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
packet switching, flow control, on-chip interconnects, router design |
| 1 | James Donald, Niraj K. Jha |
Reversible logic synthesis with Fredkin and Peres gates. |
JETC |
2008 |
DBLP DOI BibTeX RDF |
Quantum computing, reversible logic |
| 1 | Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha |
System-Level Dynamic Thermal Management for High-Performance Microprocessors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallav Gupta, Rui Zhang, Niraj K. Jha |
Automatic Test Generation for Combinational Threshold Logic Networks. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar 0002, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha |
A system-level perspective for efficient NoC design. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha |
Token flow control. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Prateek Mishra, Niraj K. Jha |
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Srivaths Ravi, Niraj K. Jha |
Variability-Tolerant Register-Transfer Level Synthesis. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
Dynamic Binary Instrumentation-Based Framework for Malware Defense. |
DIMVA |
2008 |
DBLP DOI BibTeX RDF |
control-data flow, execution context, dynamic binary instrumentation, virtualization, Malware |
| 1 | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Energy-optimizing source code transformations for operating system-driven embedded software. |
ACM Trans. Embedded Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Linux, energy consumption, source code transformations |
| 1 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Hybrid Simulation for Energy Estimation of Embedded Software. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Shang, Robert P. Dick, Niraj K. Jha |
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiong Luo, Niraj K. Jha |
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Niraj K. Jha |
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Automated Energy/Performance Macromodeling of Embedded Software. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Zhang, Pallav Gupta, Niraj K. Jha |
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiong Luo, Niraj K. Jha, Li-Shiuan Peh |
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Niraj K. Jha |
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar |
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallav Gupta, Niraj K. Jha, Loganathan Lingappan |
A Test Generation Framework for Quantum Cellular Automata Circuits. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee |
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Niraj K. Jha |
Editorial. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Architectural Support for Run-Time Validation of Program Data Properties. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha |
Express virtual channels: towards the ideal interconnection fabric. |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
packet-switching, flow-control, router design |
| 1 | Wei Zhang 0012, Li Shang, Niraj K. Jha |
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha |
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Energy and execution time analysis of a software-based trusted platform module. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Niket Agarwal, Niraj K. Jha |
CMOS logic design with independent-gate FinFETs. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha |
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha |
Temperature-Aware On-Chip Networks. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
Temperature-aware, thermal management, thermal modeling, on-chip networks, thermal, simulation framework |
| 1 | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
RTL-Aware Cycle-Accurate Functional Power Estimation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Application-specific heterogeneous multiprocessor synthesis using extensible processors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Use of Computation-Unit Integrated Memories in High-Level Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Shang, Li-Shiuan Peh, Niraj K. Jha |
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallav Gupta, Abhinav Agrawal, Niraj K. Jha |
An Algorithm for Synthesis of Reversible Logic Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar |
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha |
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. |
IEEE Trans. Mob. Comput. |
2006 |
DBLP DOI BibTeX RDF |
energy analysis, security, embedded system, low-power, AES, RSA, security protocols, ECC, DES, handheld, SSL, Diffie-Hellman, DSA, cryptographic algorithms, 3DES |
| 1 | Lin Zhong, Niraj K. Jha |
Dynamic Power Optimization Targeting User Delays in Interactive Systems. |
IEEE Trans. Mob. Comput. |
2006 |
DBLP DOI BibTeX RDF |
human-computer interaction, user interfaces, Energy efficiency, power management |
| 1 | Keith S. Vallerio, Lin Zhong, Niraj K. Jha |
Energy-Efficient Graphical User Interface Design. |
IEEE Trans. Mob. Comput. |
2006 |
DBLP DOI BibTeX RDF |
low power, Graphical user interfaces, handheld computers |
| 1 | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
A Scalable Synthesis Methodology for Application-Specific Processors. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Zhang, Niraj K. Jha |
Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhang 0012, Niraj K. Jha, Li Shang |
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
NRAM, logic folding, run-time reconfiguration |
| 1 | Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha |
HybDTM: a coordinated hardware-software approach for dynamic thermal management. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
hybrid hardware-software management, thermal model, dynamic thermal management |
| 1 | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar |
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
computation offloading, software partitioning |
| 1 | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security |
| 1 | Loganathan Lingappan, Niraj K. Jha |
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Zhang, Niraj K. Jha |
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Architectures for efficient face authentication in embedded systems. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallav Gupta, Niraj K. Jha, Loganathan Lingappan |
Test generation for combinational quantum cellular automata (QCA) circuits. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee |
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Active Learning Driven Data Acquisition for Sensor Networks. |
ISCC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
Architectural support for safe software execution on embedded processors. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
type safety, memory safety, extensible processors |
| 1 | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
Energy macromodeling of embedded operating systems. |
ACM Trans. Embedded Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Linux, energy consumption, characterization |
| 1 | Yunsi Fei, Niraj K. Jha |
Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. |
IJES |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha |
Threshold network synthesis and optimization and its application to nanotechnologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Zhong, Niraj K. Jha |
Interconnect-aware low-power high-level synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Le Yan, Jiong Luo, Niraj K. Jha |
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
Generation of distributed logic-memory architectures through high-level synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
Input space-adaptive optimization for embedded-software synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
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