Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Li-Wei Wu, Wei-Xiang Tang, Yarsun Hsu	A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip.	ISPA	2011	DBLP DOI BibTeX RDF	north-last weave, dynamic reconfigurable, NoC
1	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
1	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
1	Wooyoung Jang, David Z. Pan	Application-aware NoC design for efficient SDRAM access.	DAC	2010	DBLP DOI BibTeX RDF	QoS, memory, flow control, router, NoC, on-chip communication
1	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
1	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
1	Jueping Cai, Zheng Liu, Ming Du, Zan Li, Lei Yao	Integrated Modeling, Generation and Optimization for Packet based NoC Topology.	AINA	2010	DBLP DOI BibTeX RDF	Optimization, NoC, Topology modeling
1	Khalid Latif 0002, Tiberiu Seceleanu, Hannu Tenhunen	Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers.	ECBS	2010	DBLP DOI BibTeX RDF	Segbus, Virtual Channel, NoC
1	Chi-Chia Sun, Jürgen Götze, Hong-Yuan Jheng, Shanq-Jang Ruan	Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA.	CIT	2010	DBLP DOI BibTeX RDF	SMVM, SMVM-NoC, FPGA, SoC, NoC, Iterative Algorithm, Sparse Matrix
1	Dawid Zydek, Henry Selvaraj, Laxmi Gewali	Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors.	ITNG	2010	DBLP DOI BibTeX RDF	FPGA, CMP, mesh, NoC, torus, hardware implementation, processor allocator
1	Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.	NAS	2010	DBLP DOI BibTeX RDF	non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through
1	Jonas Diemer, Rolf Ernst	Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Latency-Sensitive, Quality of Service, QoS, Real-Time, NoC, Manycore
1	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
1	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
1	Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi	Investigation of Transient Fault Effects in an Asynchronous NoC Router.	PDP	2010	DBLP DOI BibTeX RDF	Fault Tolerance, Asynchronous, NoC
1	Alpesh Patel, Hemangee K. Kapoor	Exploring Use of NoC for Reconfigurable Video Coding.	VLSI Design	2010	DBLP DOI BibTeX RDF	Reconfigurable Video Coding, MPEG RVC, Network on Chip, NoC
1	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
1	Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang	No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.	DAC	2009	DBLP DOI BibTeX RDF	level-1 non-uniform cache architecture, ring interconnection, single-cycle transactions, multi-core, NOC, SOC, arbitration, memory structure
1	Mahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara	Dynamic thread and data mapping for NoC based CMPs.	DAC	2009	DBLP DOI BibTeX RDF	mapping, dynamic, CMP, thread, NoC, data
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	NoC topology synthesis for supporting shutdown of voltage islands in SoCs.	DAC	2009	DBLP DOI BibTeX RDF	shutdown, topology, NoC, leakage power, voltage islands
1	Eby G. Friedman	Design challenges in high performance three-dimensional circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	VLSI, NOC, 3-D, clock distribution
1	Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper	Multicast routing with dynamic packet fragmentation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	on-chip router, interconnection network, NoC
1	Ling Wang, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen	Router with centralized buffer for network-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	centralized buffer, architecture, router, NoC
1	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
1	Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using NoC routers as processing elements.	SBCCI	2009	DBLP DOI BibTeX RDF	SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano	Performance Analysis of ClearSpeed's CSX600 Interconnects.	ISPA	2009	DBLP DOI BibTeX RDF	ClearSpeed, CSX600, performance evaluation, SIMD, NoC
1	Ashwini Raina, Venkatesan Muthukumar	Traffic Aware Scheduling Algorithm for Network on Chip.	ITNG	2009	DBLP DOI BibTeX RDF	Scheduling, Mapping, NoC, Simulation framework
1	Ashwini Raina, Venkatesan Muthukumar	Fuse-N: Framework for Unified Simulation Environment for Network-on-Chip.	ITNG	2009	DBLP DOI BibTeX RDF	task scheduling and mapping, NoC, Simulation framework
1	Ling Wang, Jianye Hao, Feixuan Wang	Bus-Based and NoC Infrastructure Performance Emulation and Comparison.	ITNG	2009	DBLP DOI BibTeX RDF	Spidernet, FPGA, NoC
1	Dawid Zydek, Henry Selvaraj	Processor Allocation Problem for NoC-Based Chip Multiprocessors.	ITNG	2009	DBLP DOI BibTeX RDF	allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques
1	Xu Wang, Ge Gan, Dongrui Fan, Shuxu Guo	GFFC: The Global Feedback Based Flow Control in the NoC Design for Many-core Processor.	NPC	2009	DBLP DOI BibTeX RDF	global feedback, flow control, NoC, many-core
1	Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy	New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	FPGA, NoC, SDR, Partial Reconfiguration
1	Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick	Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	asynchronous FIFO, FPGA, grid, dynamic reconfiguration, NoC, run-time reconfiguration
1	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
1	Oreste Villa, Gianluca Palermo, Cristina Silvano	Efficiency and scalability of barrier synchronization on NoC based many-core architectures.	CASES	2008	DBLP DOI BibTeX RDF	scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore
1	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.	DAC	2008	DBLP DOI BibTeX RDF	flexible LDPC decoder, multiprocessor, NoC, de Bruijn graph
1	Xianfang Tan, Lei Zhang 0014, Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Yulu Yang	Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	QRDT, routing algorithm, router, NOC
1	Mahmut T. Kandemir, Ozcan Ozturk	Software-directed combined cpu/link voltage scaling fornoc-based cmps.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	compiler, CMP, NoC, voltage scaling, cpu, communication link
1	Daniel Greenfield, Simon W. Moore	Fractal communication in software data dependency graphs.	SPAA	2008	DBLP DOI BibTeX RDF	CMP, communication complexity, fractal, NoC
1	Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong	Power-Aware Test Framework for Network-on-Chip.	ICONS	2008	DBLP DOI BibTeX RDF	test, low-power, NoC
1	Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser	Using an MDE Approach for Modeling of Interconnection Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	UML2 Templates, SoC, MINs, NoC, MDE, MARTE, Delta Networks
1	Yaoting Jiao, Mei Yang, Yingtao Jiang, Yulu Yang, Xiao-chun Yun	Deadlock-Free Multi-Path Routing for Torus-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	deadlock, NoC, MPR
1	Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun	Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	PRDT, router, NoC
1	Itamar Cohen, Ori Rottenstreich, Isaac Keslassy	Statistical Approach to NoC Design.	NOCS	2008	DBLP DOI BibTeX RDF	T-Plot, NoC, statistical approach, capacity allocation, traffic matrices
1	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
1	Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.	NOCS	2008	DBLP DOI BibTeX RDF	DSPIN, ANOC, physical implementation, FAUST, bi-synchronous FIFO, network-on-chip, NoC
1	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
1	Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo	A Fast Emulation-Based NoC Prototyping Framework.	ReConFig	2008	DBLP DOI BibTeX RDF	Partial Reconfiguratin, FPGA, Rapid Prototyping, Emulation, NoC, SoC design
1	Kwang-Ting (Tim) Cheng	From the EIC.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	Chris Rowen, runtime power monitoring, NoC, hybrid approach, simultaneous switching noise, RFIC
1	John Mark Nolen, Rabi N. Mahapatra	Time-Division-Multiplexed Test Delivery for NoC Systems.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	scan test delivery, SoC, NoC, TAM, time-division multiplexing, test access mechanism, embedded-core testing, TDM
1	Samuel Evain, Jean-Philippe Diguet	Efficient space-time noc path allocation based on mutual exclusion and pre-reservation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	guarantied traffic, path allocation, NOC, CAD tool
1	Praveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra	SAPP: scalable and adaptable peak power management in nocs.	ISLPED	2007	DBLP DOI BibTeX RDF	network-on-chip, NoC, peak power
1	Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner	A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	energy, MPSoC, NoC, task migration, memory organization
1	Christophe Bobda, Thomas Haller, Felix Mühlbauer, Dennis Rech, Simon Jung	Design of adaptive multiprocessor on chip systems.	SBCCI	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurability, MPSoC, NoC
1	Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva	Cache coherency communication cost in a NoC-based MPSoC platform.	SBCCI	2007	DBLP DOI BibTeX RDF	cache coherence, MPSoC, NoC, directory
1	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
1	Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici	DATE 07 workshop on diagnostic services in NoCs.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	diagnostic services, DATE 2007, network on chip, NoC
1	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs.	DAC	2006	DBLP DOI BibTeX RDF	application-specific designs, low-power, NOC, SOC
1	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Compiler-directed channel allocation for saving power in on-chip networks.	POPL	2006	DBLP DOI BibTeX RDF	compiler, energy consumption, NoC
1	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
1	Grant Martin	Book Reviews: NoC, NoC ... Who's there?	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	technology and tools, networks, NoC
1	Shyam R. Chidamber, David P. Darcy, Chris F. Kemerer	Managerial Use of Metrics for Object-Oriented Software: An Exploratory Analysis.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	SLOC, WMC, DIT, LCOM, CBO, RFC, design, object-orientation, reuse, project management, Software metrics, productivity, NOC, programmer, effort