Search results for "Norman P. Jouppi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber	Improving System Energy Efficiency with Memory Rank Subsetting.	TACO	2012	DBLP DOI BibTeX RDF
1	Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi	CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory.	DATE	2012	DBLP BibTeX RDF
1	Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.	HPCA	2012	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi	Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.	TACO	2011	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	DRAM errors in the wild: technical perspective.	Commun. ACM	2011	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar	Multi-Core Cache Hierarchies		2011	DOI RDF
1	Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn	The role of optics in future high radix switch design.	ISCA	2011	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi	System implications of memory reliability in exascale computing.	SC	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi	System-level integrated server architectures for scale-out datacenters.	MICRO	2011	DBLP DOI BibTeX RDF
1	Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie	Design implications of memristor-based RRAM cross-point structures.	DATE	2011	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez	FREE-p: Protecting non-volatile memory against both hard and soft errors.	HPCA	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi	CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Rethinking DRAM design and organization for energy-constrained multi-cores.	ISCA	2010	DBLP DOI BibTeX RDF	chipkill, dram architecture, subarrays, energy-efficiency, locality
1	Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.	SC	2010	DBLP DOI BibTeX RDF
1	Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber, Norman P. Jouppi	Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08).	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Huei Pei Kuo, Joseph Straznicky, Norman P. Jouppi, Shih-Yuan Wang	A High-Speed Optical Multidrop Bus for Computer Interconnections.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Technical perspective - Software and hardware support for deterministic replay of parallel programs.	Commun. ACM	2009	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie	Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.	SC	2009	DBLP DOI BibTeX RDF
1	Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber	Future scaling of processor-memory interfaces.	SC	2009	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Yuan Xie	Emerging technologies and their impact on system design.	ISLPED	2009	DBLP DOI BibTeX RDF	new non-volatile memory technology, emerging technology, 3d integration
1	Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Resilience Challenges for Exascale Systems.	DFT	2009	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Norman P. Jouppi, Yuan Xie	PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.	ICCAD	2009	DBLP BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07).	SIGARCH Computer Architecture News	2008	DBLP DOI BibTeX RDF
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Architecting Efficient Interconnects for Large Caches with CACTI 6.0.	IEEE Micro	2008	DBLP DOI BibTeX RDF	CACTI 6.0, on-chip interconnects, cache design
1	Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi	A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn	Corona: System Implications of Emerging Nanophotonic Technology.	ISCA	2008	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	System implications of integrated photonics.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan	Implementing high availability memory with a duplication cache.	MICRO	2008	DBLP DOI BibTeX RDF
1	Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals	A High-Speed Optical Multi-Drop Bus for Computer Interconnections.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
1	Raymond G. Beausoleil, Jung Ho Ahn, Nathan L. Binkert, Al Davis, David Fattal, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, C. M. Santori, Robert S. Schreiber, S. M. Spillane, Dana Vantrease, Q. Xu	A Nanophotonic Interconnect for High-Performance Many-Core Computation.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi	Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06).	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith	Isolation in Commodity Multicore Processors.	IEEE Computer	2007	DBLP DOI BibTeX RDF	chip multiprocessors, multicore processors, fault isolation
1	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
1	Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi	High-performance ethernet-based communications for future multi-core processors.	SC	2007	DBLP DOI BibTeX RDF
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
1	Shekhar Borkar, Norman P. Jouppi, Per Stenström	Microprocessors in the era of terascale integration.	DATE	2007	DBLP DOI BibTeX RDF
1	Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi	Architecture - The potential energy efficiency of vector acceleration.	SC	2006	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi	Core architecture optimization for heterogeneous chip multiprocessors.	PACT	2006	DBLP DOI BibTeX RDF	computer architecture, multi-core architectures, heterogeneous chip multiprocessors
1	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder	Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.	MICRO	2006	DBLP DOI BibTeX RDF
1	Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair	Improving the performance and power efficiency of shared helpers in CMPs.	CASES	2006	DBLP DOI BibTeX RDF	constructive sharing, factored core, flexible sharing, helper configuration, helper engine, sharing policy, CMP, phase
1	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker	Fast synchronization for chip multiprocessors.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood	Dynamically configurable shared CMP helper engines for improved performance.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan	Heterogeneous Chip Multiprocessors.	IEEE Computer	2005	DBLP DOI BibTeX RDF	Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
1	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Stan Thomas	Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation.	ICRA	2005	DBLP BibTeX RDF
1	Parthasarathy Ranganathan, Norman P. Jouppi	Enterprise IT Trends and Implications for Architecture Research.	HPCA	2005	DBLP DOI BibTeX RDF
1	Jean-Francois Collard, Norman P. Jouppi, Sami Yehia	System-wide performance monitors and their application to the optimization of coherent memory accesses.	PPOPP	2005	DBLP DOI BibTeX RDF	coherence traffic, performance monitors
1	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	HiPC	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.	ISCA	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Subu Iyer, Wayne Mack, April Slayden Mitchell, Stan Thomas	A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking.	ICRA	2004	DBLP DOI BibTeX RDF
1	Jacob Augustine, Shivarama Rao, Norman P. Jouppi, Subu Iyer	Region of interest editing of MPEG-2 video streams in the compressed domain.	ICME	2004	DBLP BibTeX RDF
1	Norman P. Jouppi, Subu Iyer, Stan Thomas, April Slayden	BiReality: mutually-immersive telepresence.	ACM Multimedia	2004	DBLP DOI BibTeX RDF	robotics, computer-supported collaborative work, video conferencing, video mediated communication, spatial audio, audio conferencing
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.	Computer Architecture Letters	2003	DBLP DOI BibTeX RDF	chip multiprocessor, low-power architecture
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.	MICRO	2003	DBLP DOI BibTeX RDF
1	M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	instruction queue clock rate, Pipelining
1	Norman P. Jouppi	First steps towards mutually-immersive mobile telepresence.	CSCW	2002	DBLP DOI BibTeX RDF	multi-channel audio, multi-user networked applications, multimedia, robotics, haptics, video conferencing, human visual perception, audio conferencing, user interface hardware
1	Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi	Reconfigurable caches and their application to media processing.	ISCA	2000	DBLP DOI BibTeX RDF
1	Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic	The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.	International Journal of Parallel Programming	1999	DBLP DOI BibTeX RDF
1	Joel McCormack, Ronald N. Perry, Keith I. Farkas, Norman P. Jouppi	Feline: Fast Elliptical Lines for Anisotropic Texture Mapping.	SIGGRAPH	1999	DBLP DOI BibTeX RDF	space-variant filtering, texture mapping, anisotropic filtering
1	Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi	Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions.	ISCA	1999	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic	Memory-System Design Considerations for Dynamically-Scheduled Processors.	ISCA	1997	DBLP DOI BibTeX RDF
1	Subbarao Palacharla, Norman P. Jouppi, James E. Smith	Complexity-Effective Superscalar Processors.	ISCA	1997	DBLP DOI BibTeX RDF
1	Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic	The Multicluster Architecture: Reducing Cycle Time Through Partitioning.	MICRO	1997	DBLP BibTeX RDF	partitioned architecture, static instruction scheduling, register allocation, decentralized architecture
1	Keith I. Farkas, Norman P. Jouppi, Paul Chow	Register File Design Considerations in Dynamically Scheduled Processors.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic scheduling, register files, register renaming
1	Keith I. Farkas, Norman P. Jouppi, Paul Chow	How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?	HPCA	1995	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Steven J. E. Wilton	Tradeoffs in Two-Level On-Chip Caching.	ISCA	1994	DBLP DOI BibTeX RDF
1	Keith I. Farkas, Norman P. Jouppi	Complexity/Performance Tradeoffs with Non-Blocking Loads.	ISCA	1994	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Cache Write Policies and Performance.	ISCA	1993	DBLP DOI BibTeX RDF
1	J. Bradley Chen, Anita Borg, Norman P. Jouppi	A Simulation Based Study of TLB Performance.	ISCA	1992	DBLP DOI BibTeX RDF
1	John L. Hennessy, Norman P. Jouppi	Computer Technology and Architecture: An Evolving Interaction.	IEEE Computer	1991	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.	ISCA	1990	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1
1	Norman P. Jouppi	Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU.	ISCA	1989	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Jonathan Bertoni, David W. Wall	A Unified Vector/Scalar Floating-Point Architecture.	ASPLOS	1989	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, David W. Wall	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.	ASPLOS	1989	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Timing Analysis and Performance Improvement of MOS VLSI Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1987	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Derivation of Signal Flow Direction in MOS VLSI.	IEEE Trans. on CAD of Integrated Circuits and Systems	1987	DBLP DOI BibTeX RDF
1	Norman P. Jouppi	Timing analysis for nMOS VLSI.	DAC	1983	DBLP BibTeX RDF
1	John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill	Hardware/Software Tradeoffs for Increased Performance.	ASPLOS	1982	DBLP DOI BibTeX RDF
1	John L. Hennessy, Norman P. Jouppi, John Gill, Forest Baskett, Alex Strong, Thomas R. Gross, Christopher Rowen, Judson Leonard	The MIPS Machine.	COMPCON	1982	DBLP BibTeX RDF

Publications of "Norman P. Jouppi" ( http://dblp.L3S.de/Authors/Norman_P._Jouppi )