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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 55 publication records. Showing 55 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto |
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto |
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa |
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Scan-based attack against elliptic curve cryptosystems. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
State-dependent changeable scan architecture against scan-based side channel attacks. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A Scan-Based Attack Based on Discriminators for AES Cryptosystems. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A Two-Level Cache Design Space Exploration System for Embedded Applications. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An L1 Cache Design Space Exploration System for Embedded Applications. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Design-for-secure-test for crypto cores. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Exact and fast L1 cache simulation for embedded systems. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A Secure Test Technique for Pipelined Advanced Encryption Standard. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
GECOM: Test data compression combined with all unknown response masking. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Power-efficient LDPC code decoder architecture. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
FIFO buffer, LDPC decoder, intermediate message compression technique, message-passing schedule, clock gating |
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Memory-Efficient Accelerating Schedule for LDPC Decoder. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
A parallel LSI architecture for LDPC decoder improving message-passing schedule. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura |
Low Power Test Compression Technique for Designs with Multiple Scan Chain. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Reconfigurable adaptive FEC system with interleaving. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A processor core synthesis system in IP-based SoC design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa |
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
Instruction set and functional unit synthesis for SIMD processor cores. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A thread partitioning algorithm in low power high-level synthesis. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
VLSI Architecture for a Flexible Motion Estimation with Parameters. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Motion estimation, VHDL, Block matching |
| 1 | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Area/delay estimation for digital signal processor cores. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki |
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki |
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. |
Journal of Circuits, Systems, and Computers |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki |
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki |
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki |
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
A Simultaneous Placement and Global Routing Algorithm for FPGAs. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
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