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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 32 occurrences of 27 keywords
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Results
Found 56 publication records. Showing 56 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Dennis Nienhüser, Tobias Bär, Ralf Kohlhaas, Thomas Schamm, Jochen Zimmermann, Thomas Gumpp, Marcus Strand, Oliver Bringmann, Johann Marius Zöllner |
Energy Efficient Driving and Operation Strategies Based on Situation Awareness and Reasoning.  |
it - Information Technology  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel |
Analysis of multi-domain scenarios for optimized dynamic power management strategies. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Stefan Stattelmann, Gernot Gebhard, Christoph Cullmann, Oliver Bringmann, Wolfgang Rosenstiel |
Hybrid source-level simulation of data caches using abstract cache models. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Kosmas Knoedler, Jochen Steinmann, Sylvain Laversanne, Stephen Jones, Arno Huss, Emre Kural, David Sanchez, Oliver Bringmann, Jochen Zimmermann |
Optimal energy management and recovery for FEV. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Andreas Bernauer, Johannes Zeppenfeld, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel |
Combining Software and Hardware LCS for Lightweight On-chip Learning. |
Organic Computing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf |
Autonomic System on Chip Platform. |
Organic Computing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf |
Applying ASoC to Multi-core Applications for Workload Management. |
Organic Computing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel |
Fast and accurate source-level simulation of software timing considering complex code optimizations. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Bernauer, Gunnar Arndt, Oliver Bringmann, Wolfgang Rosenstiel |
Autonomous multi-processor-SoC optimization with distributed learning classifier systems XCS. |
ICAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel |
Fast and accurate resource conflict simulation for performance analysis of multi-core systems. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Allan Crone, Oliver Bringmann, C. Chevallaz, B. Dickman, Volkan Esen, M. Rohleder |
State of the art verification methodologies in 2015. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel |
Dominator homomorphism based code matching for source-level simulation of embedded software. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich |
Design and architectures for dependable embedded systems. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Stattelmann, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel |
Reconstructing Line References from Optimized Binary Code for Source-Level Annotation. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Andreas Bernauer, Johannes Zeppenfeld, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel |
Combining Software and Hardware LCS for Lightweight On-Chip Learning. |
DIPES/BICC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Matthias Müller, Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel, Dennis Nienhüser, Johann Marius Zöllner, Oliver Bringmann |
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Andreas Braun, Oliver Bringmann, Djones Lettnin, Wolfgang Rosenstiel |
Simulation-based verification of the MOST NetInterface specification revision 3.0. |
DATE |
2010 |
DBLP BibTeX RDF |
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| 1 | Barbara Rakitsch, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel |
Pruning population size in XCS for complex problems. |
IJCNN |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel |
Generic Self-Adaptation to Reduce Design Effort for System-on-Chip. |
SASO |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel |
Network-on-Chip Architecture Exploration Framework. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Viehl, Michael Pressler, Oliver Bringmann, Wolfgang Rosenstiel |
White box performance analysis considering static non-preemptive software scheduling. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Björn Sander, Jürgen Schnerr, Oliver Bringmann |
ESL power analysis of embedded processors for temperature and reliability estimations. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
reliability, power analysis, temperature, electronic system level |
| 1 | Alexander Viehl, Michael Pressler, Oliver Bringmann |
Bottom-up performance analysis considering time slice based software scheduling at system level. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
scheduling, performance analysis, communicating processes |
| 1 | Jürgen Schnerr, Oliver Bringmann, Alexander Viehl, Wolfgang Rosenstiel |
High-performance timing simulation of embedded software. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
software timing, virtual prototypes, simulation acceleration |
| 1 | Alexander Viehl, Björn Sander, Oliver Bringmann, Wolfgang Rosenstiel |
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jochen Zimmermann, Oliver Bringmann, Joachim Gerlach, Florian Schaefer, Ulrich Nageldinger |
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Krause, Dominik Englert, Oliver Bringmann, Wolfgang Rosenstiel |
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
RTOS modeling, embedded systems, instruction set simulation |
| 1 | Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel |
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel |
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Axel Siebenborn, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel |
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Krause, Oliver Bringmann, André Hergenhan, Gökhan Tabanoglu, Wolfgang Rosenstiel |
Timing simulation of interconnected AUTOSAR software-components. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel |
A Hybrid Approach for System-Level Design Evaluation. |
IESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel |
Probabilistic performance risk analysis at system-level. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
probabilistic risk quantification, performance analysis |
| 1 | Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel |
Organic Computing at the System on Chip Level. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton |
GreenBus: a generic interconnect fabric for transaction level modelling. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
SoC, SystemC, TLM, on-chip communication |
| 1 | Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele |
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. |
BICC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel |
Formal performance analysis and simulation of UML/SysML models for ESL design. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf |
An Architecture for Runtime Evaluation of SoC Reliability. |
GI Jahrestagung |
2006 |
DBLP BibTeX RDF |
|
| 1 | Matthias Krause, Oliver Bringmann, Wolfgang Rosenstiel |
Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems. |
Design Autom. for Emb. Sys. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele |
Towards a Framework and a Design Methodology for Autonomous SoC. |
ARCS Workshops |
2005 |
DBLP BibTeX RDF |
|
| 1 | Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel, Axel Siebenborn, Oliver Bringmann |
SystemC-Based Communication and Performance Analysis. |
FDL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele |
Towards a Framework and a Design Methodology for Autonomic SoC. |
ICAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel |
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn |
Conflict analysis in multiprocess synthesis for optimized system integration. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
scheduling, systems-on-chip, system level design, concurrent systems, binding, behavioral synthesis |
| 1 | Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel |
Communication Analysis for Network-on-Chip Design. |
PARELEC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel |
Communication Analysis for System-On-Chip Design. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn |
Controller Estimation for FPGA Target Architectures during High-Level Synthesis. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
FPGA, controller, high-level synthesis, area estimation |
| 1 | Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel |
Worst-case performance analysis of parallel, communicating software processes. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel |
Hierarchische Synthese für anwendungsspezifische Prototypenimplementierungen (Hierarchical Synthesis for Application-Specific Prototyping Implementations). |
it+ti - Informationstechnik und Technische Informatik |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn |
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann |
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL |
| 1 | Oliver Bringmann, Wolfgang Rosenstiel |
Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen. |
GI Jahrestagung |
1999 |
DBLP BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt |
Synchronization Detection for Multi-Process Hierarchical Synthesis. (PDF / PS) |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Bringmann, Wolfgang Rosenstiel |
Cross-Level Hierarchical High-Level Synthesis. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Hierarchical Synthesis, Complex Components, High-Level Synthesis |
| 1 | Oliver Bringmann, Wolfgang Rosenstiel |
Resource sharing in hierarchical synthesis. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Hierarchical Synthesis, High-Level Synthesis, Resource Sharing |
| 1 | Ulrich Weinmann, Oliver Bringmann, Wolfgang Rosenstiel |
Device selection for system partitioning. |
EURO-DAC |
1995 |
DBLP DOI BibTeX RDF |
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