| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. López, David Novo |
Quantization of VLSI digital signal processing systems.  |
EURASIP J. Adv. Sig. Proc.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys |
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. |
ACM Trans. Design Autom. Electr. Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Mahtab Alam, Olivier Berder, Daniel Menard, Olivier Sentieys |
Latency-Energy Optimized MAC Protocol for Body Sensor Networks. |
BSN |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien |
A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. |
J. Low Power Electronics |
2011 |
DBLP BibTeX RDF |
|
| 1 | Tuan-Duc Nguyen, Olivier Berder, Olivier Sentieys |
Energy-Efficient Cooperative Techniques for Infrastructure-to-Vehicle Communications. |
IEEE Transactions on Intelligent Transportation Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Mahtab Alam, Olivier Berder, Daniel Menard, Thomas Anger, Olivier Sentieys |
A Hybrid Model for Accurate Energy Analysis of WSN Nodes. |
EURASIP J. Emb. Sys. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn |
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. |
SIGARCH Computer Architecture News |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys |
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. |
Journal of Systems Architecture - Embedded Systems Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruifeng Zhang, Jean-Marie Gorce, Olivier Berder, Olivier Sentieys |
Lower Bound of Energy-Latency Tradeoff of Opportunistic Routing in Multihop Networks. |
EURASIP J. Wireless Comm. and Networking |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthieu Texier, Raphaël David, Karim Ben Chehida, Olivier Sentieys |
Graphic rendering application profiling on a shared memory MPSOC architecture. |
DASIP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Le Quang Vinh Tran, Olivier Berder, Olivier Sentieys |
Non-regenerative full distributed space-time codes in cooperative relaying networks. |
WCNC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien |
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement |
Error recovery technique for coarse-grained reconfigurable architectures. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
Parallel Evaluation of Hopfield Neural Networks. |
IJCCI (NCTA) |
2011 |
DBLP BibTeX RDF |
|
| 1 | Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn |
Towards a power and energy efficient use of partial dynamic reconfiguration. |
ReCoSoC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Courtay, Johann Laurent, Olivier Sentieys |
Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Romuald Rocher, Daniel Menard, Olivier Sentieys, Pascal Scalart |
Accuracy evaluation of fixed-point based LMS algorithm. |
Digital Signal Processing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sébastien Pillement, Olivier Sentieys, Jean-Marc Philippe |
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys |
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". |
IEEE Communications Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys |
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement |
Design of a fault-tolerant coarse-grained. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthick Parashar, Romuald Rocher, Daniel Menard, Olivier Sentieys |
Analytical approach for analyzing quantization noise effects on decision operators. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer |
A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
Task placement for dynamic and partial reconfigurable architecture. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Olivier Berder, Olivier Sentieys |
PowWow : Power Optimized Hardware/Software Framework for Wireless Motes. |
ARCS Workshops |
2010 |
DBLP BibTeX RDF |
|
| 1 | Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys |
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys |
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
WSN node, hardware specialization, microcoded architecture, low-power design |
| 1 | Karthick Parashar, Romuald Rocher, Daniel Menard, Olivier Sentieys |
A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Wordlength Optimization, Quantization Noise, System, Roundoff errors, Fixed point arithmetic |
| 1 | Karthick Parashar, Daniel Menard, Romuald Rocher, Olivier Sentieys, David Novo, Francky Catthoor |
Fast performance evaluation of fixed-point systems with un-smooth operators. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuan-Duc Nguyen, Olivier Berder, Olivier Sentieys |
Cooperative MISO and Relay Comparison in Energy Constrained WSNs. |
VTC Spring |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Renaud Santoro, Olivier Sentieys, Sébastien Roy |
On-the-Fly Evaluation of FPGA-Based True Random Number Generator. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Julien Lallet, Sébastien Pillement, Olivier Sentieys |
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Quoc-Tuong Ngo, Olivier Berder, Baptiste Vrigneau, Olivier Sentieys |
Minimum Distance Based Precoder for MIMO-OFDM Systems Using a 16-QAM Modulation. |
ICC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai-Nam Nguyen, Daniel Menard, Olivier Sentieys |
Dynamic Precision Scaling for Low Power WCDMA Receiver. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Renaud Santoro, Olivier Sentieys, Sébastien Roy |
On-line Monitoring of Random Number Generators for Embedded Security. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys |
Ultra Low-power FSM for Control Oriented Applications. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David |
Reconfigurable Operator Based Multimedia Embedded Processor. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Courtay, Olivier Sentieys, Johann Laurent, Nathalie Julien |
High-Level Interconnect Delay and Power Estimation. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sébastien Pillement, Olivier Sentieys, Raphaël David |
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency. |
EURASIP J. Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Romain Serizel, Romuald Rocher, Olivier Sentieys |
Accuracy Constraint Determination in Fixed-Point System Design. |
EURASIP J. Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Chillet, Raphaël David, E. Grâce, Olivier Sentieys |
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. |
Technique et Science Informatiques |
2008 |
DBLP BibTeX RDF |
|
| 1 | Daniel Menard, Romuald Rocher, Olivier Sentieys |
Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien |
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Julien Lallet, Sébastien Pillement, Olivier Sentieys |
Efficient dynamic reconfiguration for multi-context embedded FPGA. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
FPGA, dynamic reconfiguration, multi-context |
| 1 | Tuan-Duc Nguyen, Olivier Berder, Olivier Sentieys |
Impact of Transmission Synchronization Error and Cooperative Reception Techniques on the Performance of Cooperative MIMO Systems. |
ICC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuan-Duc Nguyen, Olivier Berder, Olivier Sentieys |
Efficient Space Time Combination Technique for Unsynchronized Cooperative Miso Transmission. |
VTC Spring |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement |
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. |
ARCS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Hervé, Daniel Menard, Olivier Sentieys |
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. |
IJCNN |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuan-Duc Nguyen, Olivier Berder, Olivier Sentieys |
Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks. |
VTC Spring |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Daniel Chillet, Olivier Sentieys |
Floating-to-Fixed-Point Conversion for Digital Signal Processors. |
EURASIP J. Adv. Sig. Proc. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Romuald Rocher, Daniel Menard, Nicolas Hervé, Olivier Sentieys |
Fixed-Point Configurable Hardware Components. |
EURASIP J. Emb. Sys. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys |
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Romuald Rocher, Nicolas Hervé, Daniel Menard, Olivier Sentieys |
Fixed-point configurable hardware components for adaptive filters. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys |
An energy-efficient ternary interconnection link for asynchronous systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Stéphane Chevobbe, Raphaël David, Frédéric Blanc, Thierry Collette, Olivier Sentieys |
Control Unit for Parallel Embedded System. |
ReCoSoC |
2006 |
DBLP BibTeX RDF |
|
| 1 | Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys |
A low-power and high-speed quaternary interconnection link using efficient converters. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys |
Co-Design of Massively Parallel Embedded Processor Architectures. |
ReCoSoC |
2005 |
DBLP BibTeX RDF |
|
| 1 | Joel Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani |
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Olivier Sentieys |
DSP Code Generation with Optimized Data Word-Length Selection. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys |
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. |
Technique et Science Informatiques |
2003 |
DBLP BibTeX RDF |
|
| 1 | E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson |
MVL circuit design and characterization at the transistor level using SUS-LOC. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sébastien Pillement, Daniel Chillet, Olivier Sentieys |
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
A Compilation Framework for a Dynamically Reconfigurable Architecture. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. (PDF / PS) |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys |
Automatic floating-point to fixed-point conversion for DSP code generation. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point |
| 1 | Daniel Menard, Olivier Sentieys |
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys |
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. |
VLSI-SOC |
2001 |
DBLP BibTeX RDF |
|
| 1 | Jean-Philippe Diguet, Daniel Chillet, Olivier Sentieys |
A Framework for High Level Estimations of Signal Processing VLSI Implementations. |
VLSI Signal Processing |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Chillet, Olivier Sentieys, Michel Corazza |
Memory Unit Design for Real Time DSP Applications. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | J. O. Dedou, Daniel Chillet, Olivier Sentieys |
Behavioral synthesis of asynchronous systems: a methodology. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Michel Auguin, Mohamed Belhadj, Judith Benzakki, C. Carrière, Guy Durrieu, Thierry Gautier, Michel Israël, Paul Le Guernic, Michel Lemaître, E. Martin, P. Quinton, Laurence Rideau, François Rousseau, Olivier Sentieys |
Towards a multi-formalism framework for architectural synthesis: the ASAR project. |
CODES |
1994 |
DBLP DOI BibTeX RDF |
|
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