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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 88 occurrences of 53 keywords
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Results
Found 80 publication records. Showing 80 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt |
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems.  |
ACM Trans. Comput. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
Bottleneck identification and scheduling in multithreaded applications. |
ASPLOS |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai |
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter |
Thread Cluster Memory Scheduling. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt |
Data Marshaling for Multicore Systems. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yale N. Patt, Onur Mutlu |
Top Picks [Guest editors' introduction]. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das |
Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt |
Prefetch-Aware Memory Controllers. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
prefetching, DRAM, Memory systems, memory controllers, multi-core systems |
| 1 | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu |
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees. |
ISCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt |
Prefetch-aware shared resource management for multi-core systems. |
ISCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Papamichael, James C. Hoe, Onur Mutlu |
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. |
NOCS |
2011 |
DBLP BibTeX RDF |
|
| 1 | Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt |
Improving GPU performance via large warps and two-level warp scheduling. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda |
Reducing memory interference in multicore systems via application-aware memory channel partitioning. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt |
Parallel application memory scheduling. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu |
Memory systems in the many-core era: challenges, opportunities, and solution directions. |
ISMM |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, Onur Mutlu |
Memory power management via dynamic voltage/frequency scaling. |
ICAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Licheng Chen, Yongbing Huang, Yungang Bao, Onur Mutlu, Guangming Tan, Mingyu Chen |
Poster: revisiting virtual channel memory for performance and fairness on multi-core architecture. |
ICS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris Fallin, Chris Craik, Onur Mutlu |
CHIPPER: A low-complexity bufferless deflection router. |
HPCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt |
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
heterogeneous cores, parallel programming, CMP, multicore, locks, critical sections, serialization |
| 1 | Benjamin C. Lee, Ping Zhou, Jun Yang 0002, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger |
Phase-Change Technology and the Future of Main Memory. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
energy efficiency, memory architecture, DRAM, technology scaling, phase-change memory, PCM |
| 1 | Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger |
Phase change memory architecture and the quest for scalability. |
Commun. ACM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Boris Grot, Stephen W. Keckler, Onur Mutlu |
Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors. |
ISCA Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt |
Data marshaling for multi-core architectures. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
staged execution, pipelining, cmp, critical sections |
| 1 | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das |
Aérgia: exploiting packet latency slack in on-chip networks. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks |
| 1 | George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu |
Next generation on-chip networks: what kind of congestion control do we need? |
HotNets |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu |
QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors. |
NOCS |
2010 |
DBLP DOI BibTeX RDF |
Self-Similar Stochastic Processes, Multi-fractal Analysis, Networks-on-Chip, Chip Multi-Processors |
| 1 | Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero |
Efficient runahead threads. |
PACT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt |
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
fairness, shared memory systems, system performance, multi-core systems |
| 1 | Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter |
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. |
MICRO |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra |
Concurrent autonomous self-test for uncore components in system-on-chips. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter |
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. |
HPCA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Thomas Moscibroda |
Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers. |
IEEE Micro |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco |
A Flexible Software-Based Framework for Online Detection of Hardware Defects. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn |
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | José A. Joao, Onur Mutlu, Yale N. Patt |
Flexible reference-counting-based hardware acceleration for garbage collection. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
garbage collection, reference counting |
| 1 | Thomas Moscibroda, Onur Mutlu |
A case for bufferless routing in on-chip networks. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
routing, multi-core, memory systems, on-chip networks |
| 1 | Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger |
Architecting phase change memory as a scalable dram alternative. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance |
| 1 | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt |
Accelerating critical section execution with asymmetric multi-core architectures. |
ASPLOS |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections |
| 1 | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt |
Coordinated control of multiple prefetchers in multi-core systems. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
prefetching, multi-core, feedback control, memory systems |
| 1 | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das |
Application-aware prioritization mechanisms for on-chip networks. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks |
| 1 | Boris Grot, Stephen W. Keckler, Onur Mutlu |
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt |
Improving memory bank-level parallelism in the presence of prefetching. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Eiman Ebrahimi, Onur Mutlu, Yale N. Patt |
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu |
Express Cube Topologies for on-Chip Interconnects. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanjing Li, Onur Mutlu, Subhasish Mitra |
Operating system scheduling for efficient online self-test in robust systems. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Sangyeun Cho, Tao Li, Onur Mutlu |
Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Thomas Moscibroda |
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. |
ISCA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana |
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. |
ISCA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt |
Improving the performance of object-oriented languages with dynamic predication of indirect jumps. |
ASPLOS |
2008 |
DBLP DOI BibTeX RDF |
dynamic predication, indirect jumps, object-oriented languages, predicated execution, virtual functions |
| 1 | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt |
Prefetch-Aware DRAM Controllers. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Onur Mutlu, Todd M. Austin |
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Moscibroda, Onur Mutlu |
Distributed order scheduling and its application to multi-core dram controllers. |
PODC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David Christie, Alan Lee, Onur Mutlu, Benjamin G. Zorn (eds.) |
4th International Symposium on Workload Characterization (IISWC 2008), Seattle, Washington, USA, September 14-16, 2008 |
IISWC |
2008 |
DBLP BibTeX RDF |
|
| 1 | Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
Performance-aware speculation control using wrong path usefulness prediction. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Dynamic Predication of Indirect Jumps. |
Computer Architecture Letters |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Dynamic Predication of Indirect Jumps. |
Computer Architecture Letters |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt |
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
dynamic predication, adaptivity, energy efficiency, pipelining, instruction level parallelism, branch prediction, predication |
| 1 | Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn |
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
devirtualization, indirect branch prediction, virtual functions |
| 1 | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt |
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco |
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Thomas Moscibroda |
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
memory latency tolerance, processors, Runahead execution |
| 1 | Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark |
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
Wish branches, wish loops, branch prediction, predicated execution |
| 1 | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
value prediction, memory-level parallelism, runahead execution, Single data stream architectures |
| 1 | Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt |
A Case for MLP-Aware Cache Replacement. |
ISCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. |
CGO |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt |
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. |
International Journal of Parallel Programming |
2005 |
DBLP DOI BibTeX RDF |
cache filtering, speculative memory references, Caches, runahead execution, cache pollution |
| 1 | Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt |
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. |
Computer Architecture Letters |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
processor performance modeling, speculative execution, runahead execution, Single data stream architectures |
| 1 | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Techniques for Efficient Processing in Runahead Execution Engines. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt |
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt |
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. |
SBAC-PAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
Understanding the effects of wrong-path memory references on processor performance. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
processor performance analysis, wrong path modeling, wrong-path memory references, speculative execution, data prefetching, execution-driven simulation, cache pollution |
| 1 | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt |
Runahead Execution: An Effective Alternative to Large Instruction Windows. |
IEEE Micro |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt |
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
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