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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 4 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto |
Buffer Planning for IP Placement Using Sliced-LFF.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto |
Novel and efficient min cut based voltage assignment in gate level. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan |
Chemical-mechanical polishing aware application-specific 3D NoC design. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
Bus via reduction based on floorplan revising. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
floorplan revising, via reduction, bus routing |
| 1 | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto |
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
floorplanner, soft modules, zero deadspace, fixed-outline |
| 1 | Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong |
An effective buffer planning algorithm for IP based fixed-outline SOC placement. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline |
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