| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar |
Online Scheduling of Dynamic Task Graphs with Communication and Contention for Multiprocessors.  |
IEEE Trans. Parallel Distrib. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan |
A dynamic assertion-based verification platform for validation of UML designs. |
ACM SIGSOFT Software Engineering Notes |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota |
Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere? |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, A. Shanker, Sujoy Ghose, P. P. Chakrabarti |
A Low-Overhead Partition-Oriented ERfair Scheduler for Hard Real-Time Embedded Systems. |
Embedded Systems Letters |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, Sujoy Ghose, P. P. Chakrabarti |
Sticky-ERfair: a task-processor affinity aware proportional fair scheduler. |
Real-Time Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, Sujoy Ghose, P. P. Chakrabarti |
A Corrigendum to: "Sticky-ERfair: a task-processor affinity aware proportional fair scheduler". |
Real-Time Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipankar Das 0002, P. P. Chakrabarti, Purnendu Sinha |
Robust embedded software design through early analysis of quality faults. |
ISEC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Satya Gautam Vadlamudi, P. P. Chakrabarti, Dipankar Das 0002, Purnendu Sinha |
A framework for early stage quality-fault tolerance analysis of embedded control systems. |
DSN |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Satya Gautam Vadlamudi, Sandip Aine, Partha Pratim Chakrabarti |
$\hbox {MAWA}^{\ast }$ - A Memory-Bounded Anytime Heuristic-Search Algorithm. |
IEEE Transactions on Systems, Man, and Cybernetics, Part B |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudip Roy, Bhargab B. Bhattacharya, Partha Pratim Chakrabarti, Krishnendu Chakrabarty |
Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Bounded delay timing analysis and power estimation using SAT. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipankar Das 0002, P. P. Chakrabarti, Rajeev Kumar |
Thermal analysis of multiprocessor SoC applications by simulation and verification. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, P. P. Chakrabarti, Sujoy Ghose |
Partition oriented frame based fair scheduler. |
J. Parallel Distrib. Comput. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar |
Heuristic search under contract. |
Computational Intelligence |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar |
Contract Search: Heuristic Search under Node Expansion Constraints. |
ECAI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti |
An analysis of breadth-first beam search using uniform cost trees. |
ISAIM |
2010 |
DBLP BibTeX RDF |
|
| 1 | Arnab Sarkar, Rahul Nanda, Sujoy Ghose, P. P. Chakrabarti |
Safe-ERfair. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
ERfair Scheduling, Overload Handling, Real-time scheduling, Imprecise Computation, Proportional Fair Scheduling |
| 1 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
| 1 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Coverage Management with Inline Assertions and Formal Test Points. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Simulation, Verification, Coverage, Test Plan |
| 1 | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti |
Adaptive parameter control of evolutionary algorithms to improve quality-time trade-off. |
Appl. Soft Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti |
Design intent coverage revisited. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Design Intent Coverage |
| 1 | Dipankar Das 0002, P. P. Chakrabarti, Rajeev Kumar |
Scenario-based timing verification of multiprocessor embedded applications. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
execution scenarios, real time systems, static timing analysis, Timing verification |
| 1 | Arnab Sarkar, Sarthak Swaroop, Sujoy Ghose, Partha Pratim Chakrabarti |
ERfair Scheduler with Processor Shutdown. |
HiPC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Chakrabarti, Sandip Aine |
New Approaches to Design and Control of Time Limited Search Algorithms. |
PReMI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Inline Assertions - Embedding Formal Properties in a Test Bench. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Pravanjan Choudhury, Rajeev Kumar, P. P. Chakrabarti |
Hybrid Scheduling of Dynamic Task Graphs with Selective Duplication for Multiprocessors under Memory and Time Constraints. |
IEEE Trans. Parallel Distrib. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Real-time and embedded systems, Scheduling and task partitioning, Real-time distributed |
| 1 | S. K. Panda, Arnab Roy 0001, P. P. Chakrabarti, Rajeev Kumar |
Simulation-based verification using Temporally Attributed Boolean Logic. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Bus verification, instruction semantics verification, interrupt testing, offline-online verification algorithm, simulation based verification, temporal logic, timing verification |
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Auxiliary state machines + context-triggered properties in verification. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Satisfiability Models for Maximum Transition Power. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan |
Cohesive Coverage Management for Simulation and Formal Property Verification. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan |
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. |
ATVA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tathagato Rai Dastidar, P. P. Chakrabarti |
A verification system for transient response of analog circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response |
| 1 | Dipankar Das 0002, P. P. Chakrabarti, Rajeev Kumar |
Functional verification of task partitioning for multiprocessor embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Containment checking, state space reduction, UML activity diagrams, multiprocessor embedded systems |
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Event propagation for accurate circuit delay calculation using SAT. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Critical delay, event propagation, SAT |
| 1 | Abhishek Somani, P. P. Chakrabarti, Amit Patra |
An Evolutionary Algorithm-Based Approach to Automated Design of Analog and RF Circuits Using Adaptive Normalized Cost Functions. |
IEEE Trans. Evolutionary Computation |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar |
An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Arnab Sinha, Pallab Dasgupta, P. P. Chakrabarti, Kaushik De |
Hardware accelerated constrained random test generation. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
BUSpec: A framework for generation of verification aids for standard bus protocol specifications. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar |
AWA* - A Window Constrained Anytime Heuristic Search Algorithm. |
IJCAI |
2007 |
DBLP BibTeX RDF |
|
| 1 | Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta |
Timing Analysis of Sequential Circuits Using Symbolic Event Propagation. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar |
Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti |
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Bounded Delay Timing Analysis Using Boolean Satisfiability. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | S. K. Panda, Arnab Roy 0001, P. P. Chakrabarti, Rajeev Kumar |
Simulation Based Verification using Temporally Attributed Boolean Logic. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar |
Frame-Based Proportional Round-Robin. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
ERfair, O(1) scheduling, real time, Proportional fairness, round-robin, virtual time |
| 1 | Arijit Mondal, P. P. Chakrabarti |
Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni |
Design-Intent Coverage - A New Paradigm for Formal Property Verification. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipankar Das 0002, Rajeev Kumar, P. P. Chakrabarti |
Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications. |
APSEC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Formal methods for checking realizability of coalitions in 3-party systems. |
MEMOCODE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta |
A Framework for Estimating Peak Power in Gate-Level Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Rahul Chaudhry, Dipankar Das 0002, Vibha Rathi, S. K. Panda, P. P. Chakrabarti |
SystemC Modeling and Validation of A RISC Processor System. |
FDL |
2006 |
DBLP BibTeX RDF |
|
| 1 | Sandip Aine, P. P. Chakrabarti, Rajeev Kumar |
Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Samik Das, P. P. Chakrabarti, Pallab Dasgupta |
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar |
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti |
What lies between design intent coverage and model checking? |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti |
Synthesis of system verilog assertions. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Somani, P. P. Chakrabarti, Amit Patra |
A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti |
Discovering the input assumptions in specification refinement coverage. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Amit Gupta, B. S. Pankaj, Mrinmoy Ghosh, P. P. Chakrabarti |
Post-compilation optimization for multiple gains with pattern matching. |
SIGPLAN Notices |
2005 |
DBLP DOI BibTeX RDF |
instruction set FSM, peephole optimization, post-compilation optimization, pattern matching |
| 1 | Arnab Roy 0001, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti |
A framework for systematic validation and debugging of pipeline simulators. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Simulation-based verification, dataflow equivalence, pipeline validation, design space exploration, instruction scheduling, pipelined architectures |
| 1 | Tathagato Rai Dastidar, P. P. Chakrabarti, Partha Ray |
A synthesis system for analog circuits based on evolutionary search and topological reuse. |
IEEE Trans. Evolutionary Computation |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti |
Adaptive Control of Anytime Algorithm Parameters. |
IICAI |
2005 |
DBLP BibTeX RDF |
|
| 1 | Sandip Aine, Rajeev Kumar, P. P. Chakrabarti |
An Adaptive Framework for Solving Multiple Hard Problems Under Time Constraints. |
CIS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti |
Multiobjective EA Approach for Improved Quality of Solutions for Spanning Tree Problem. |
EMO |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Somani, P. P. Chakrabarti, Amit Patra |
A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix |
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti |
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipankar Das 0002, Rajeev Kumar, P. P. Chakrabarti |
Dictionary Based Code Compression for Variable Length Instruction Encodings. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tathagato Rai Dastidar, P. P. Chakrabarti |
A Verification System for Transient Response of Analog Circuits Using Model Checking. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra |
Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti |
SAT based solutions for consistency problems in formal property specifications for open systems. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
The power of first-order quantification over states in branching and linear time temporal logics. |
Inf. Process. Lett. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti |
Improved Quality of Solutions for Multiobjective Spanning Tree Problem Using Distributed Evolutionary Algorithm. |
HiPC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures. |
IWDC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti |
Distributed Evolutionary Algorithm Search for Multiobjective Spanning Tree Problem. |
IWDC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
The BUSpec platform for automated generation of verification aids for standard bus protocols. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti |
Multiobjective Genetic Search for Spanning Tree Problem. |
ICONIP |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Formal Verification of Modules under Real Time Environment Constraints. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan |
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix |
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal |
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni |
Formal verification coverage: computing the coverage gap between temporal specifications. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
A Branching Time Temporal Framework for Quantitative Reasoning. |
J. Autom. Reasoning |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti |
Open computation tree logic with fairness. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Arnab Dey, Sujoy Ghose, Wolfgang Bibel |
Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques. |
IEEE Trans. Knowl. Data Eng. |
2002 |
DBLP DOI BibTeX RDF |
logic programming, heuristic search, constraint optimization |
| 1 | Anindya C. Patthak, Indrajit Bhattacharya, Anirban Dasgupta, Pallab Dasgupta, P. P. Chakrabarti |
Quantified Computation Tree Logic. |
Inf. Process. Lett. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee |
Formal verification of module interfaces against real time specifications. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal verification, temporal logic |
| 1 | Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti |
Open Computation Tree Logic for Formal Verification of Modules. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti |
Timing analysis of tree-like RLC circuits. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan |
Min-max Computation Tree Logic. |
Artif. Intell. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti |
Abstraction of word-level linear arithmetic functions from bit-level component descriptions. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti |
Symbolic verification of Boolean constraints over partially specified functions. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti |
Abstractions for model checking of event timings. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti |
Model checking on timed-event structures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | P. P. Chakrabarti |
Partial Precedence Constrained Scheduling. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
Scheduling, NP-completeness, precedence constraints, shortest-path algorithms |
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
A design space exploration scheme for data-path synthesis. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti |
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti |
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose |
Controlling State Explosion in Static Simulation by Selective Composition. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")