| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Thomas Ebi, Holm Rauchfuss, Andreas Herkersdorf, Jörg Henkel |
Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores.  |
PATMOS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo |
Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Takumi Okuhira, Tohru Ishihara |
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Henry X. F. Huang, Steven R. S. Shen, James B. Kuo |
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Georgios D. Dimou, Peter A. Beerel, Andrew Lines |
Performance-Driven Clustering of Asynchronous Circuits. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | René van Leuken, Gilles Sicard (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Francesco Zanini, David Atienza, Giovanni De Micheli |
Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelkrim Kamel Oudjida, Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain, Mohamed Lamine Berrandjia |
High-Speed and Low-Power PID Structures for Embedded Applications. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno Vaquie, Sébastien Tiran, Philippe Maurine |
A Secure D Flip-Flop against Side Channel Attacks. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli |
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija |
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel |
Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele |
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lingamneni Avinash, Christian C. Enz, Krishna V. Palem, Christian Piguet |
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris |
A Framework for Architecture-Level Exploration of 3-D FPGA Platforms. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ons Mbarek, Alain Pegatoquet, Michel Auguin |
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rene van Leuken, Tom Van Leeuwen 0002, Huib Lincklaen Arriens |
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ning Chen, Bing Li, Ulf Schlichtmann |
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alireza Khosropour, Hossein Aghababa, Ali Afzali-Kusha, Behjat Forouzandeh |
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini |
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev, Alexandre V. Bystrov |
Improving the Robustness of Self-timed SRAM to Variable Vdds. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ignacio Herrera-Alzu, Marisa López-Vallejo |
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Chaourani, Ilias Pappas, Spiros Nikolaidis, Abdoul Rjoub |
Pass Transistor Operation Modeling for Nanoscale Technologies. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann |
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ning Chen, Bing Li, Ulf Schlichtmann |
Timing Modeling of Flipflops Considering Aging Effects. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, Matteo Cacciari, Andrea Tilli, Luca Benini |
A System Level Approach to Multi-core Thermal Sensors Calibration. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Florent Ouchet, Katell Morin-Allory, Laurent Fesquet |
C-elements for Hardened Self-timed Circuits. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mariem Slimani, Fernando Silveira, Philippe Matherat |
Variability-Speed-Consumption Trade-off in Near Threshold Operation. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mostafa Kishani, Amirali Baniasadi, Hossein Pedram |
Using Silent Writes in Low-Power Traffic-Aware ECC. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres |
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | José V. Busquets-Mataix, Carlos Catalá, Antonio Martí Campoy |
Architecture Extensions for Efficient Management of Scratch-Pad Memory. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lida Ramezani |
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelkrim Kamel Oudjida, Ahmed Liacha, Mohamed Lamine Berrandjia, Rachid Tiar |
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi |
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sébastien Marchal |
Signing Off Industrial Designs on Evolving Technologies. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiyoo Itoh |
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto García Ortiz, Leandro Soares Indrusiak |
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici |
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi |
An On-Chip Flip-Flop Characterization Circuit. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José C. Monteiro |
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham |
Clock Network Synthesis with Concurrent Gate Insertion. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi |
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans |
Hermes-A - An Asynchronous NoC Router with Distributed Routing. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Victor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc |
Modeling Time Domain Magnetic Emissions of ICs. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Belleville |
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello |
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José C. Monteiro, Rene van Leuken (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev |
Self-Timed SRAM for Energy Harvesting Systems. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Gag, Tim Wegner, Dirk Timmermann |
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid |
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Renaudin |
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Laurent Maillet-Contoz |
OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCs. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | François Pêcheux, Khouloud Zine el Abidine, Alain Greiner |
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tanguy Sassolas, Nicolas Ventroux, Nassima Boudouani, Guillaume Blanc |
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann |
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold |
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Chillet |
Open-People: Open Power and Energy Optimization PLatform and Estimator. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs |
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet |
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | P. Carazo, R. Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado |
L1 Data Cache Power Reduction Using a Forwarding Predictor. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis Kouretas, Vassilis Paliouras |
Residue Arithmetic for Designing Low-Power Multiply-Add Units. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh |
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Haase, Christoph Grimm |
Power Profiling of Embedded Analog/Mixed-Signal Systems. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Monica Figueiredo, Rui L. Aguiar |
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi |
A Hardware Implementation of the User-Centric Display Energy Management. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yusuf Leblebici |
Subthreshold Circuit Design for Ultra-Low-Power Applications. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda |
Exponent Monte Carlo for Quick Statistical Circuit Simulation. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Toby Doorn, Roelof Salters |
Robust Low Power Embedded SRAM Design: From System to Memory Cell. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom English, Ka Lok Man, Emanuel M. Popovici |
BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Castro, Pilar Parra, Antonio J. Acosta |
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre, Francky Catthoor |
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall |
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard |
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Khurram Bhatti, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek |
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ritej Bachhawat, Pankaj Golani, Peter A. Beerel |
Crosstalk in High-Performance Asynchronous Designs. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Néstor Suárez, Gustavo Marrero Callicó, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo |
Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Marius Gligor, Nicolas Fournel, Frédéric Pétrot, Fabien Colas-Bigey, Anne-Marie Fouilliart, Philippe Teninge, Marcello Coppola |
Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomasz Król, Milos Krstic, Xin Fan, Eckhard Grass |
Modeling and Reducing EMI in GALS and Synchronous Systems. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara |
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija |
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Delong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev |
The Magic Rule of Tiles: Virtual Delay Insensitivity. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi |
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paulo F. Butzen, André Inácio Reis, Renato P. Ribas |
Routing Resistance Influence in Loading Effect on Leakage Analysis. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino |
Data-Driven Clock Gating for Digital Filters. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabio Frustaci, Marco Lanuzza |
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis Kouretas, Vassilis Paliouras |
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Svensson, José Monteiro (eds.) |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Howard Chen, Indira Nair |
Power Management and Its Impact on Power Supply Noise. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro |
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid |
Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hsiang Lin, James B. Kuo |
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Karimiyan Alidash, Vojin G. Oklobdzija |
Low-Power Soft Error Hardened Latch. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Pandini |
Variability in Advanced Nanometer Technologies: Challenges and Solutions. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
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