| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Sourasis Das, Ansuman Banerjee, Pallab Dasgupta |
Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Srobona Mitra, Priyankar Ghosh, Pallab Dasgupta |
Verification by parts: reusing component invariant checking results. |
IET Computers & Digital Techniques |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan |
A dynamic assertion-based verification platform for validation of UML designs. |
ACM SIGSOFT Software Engineering Notes |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Aritra Hazra, Pallab Dasgupta, Ansuman Banerjee, Kevin Harer |
Formal methods for coverage analysis of architectural power states in power-managed designs. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay |
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta |
Formal methods for ranking counterexamples through assumption mining. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Manoj G. Dixit, S. Ramesh, Pallab Dasgupta |
Some results on Parametric Temporal Logic. |
Inf. Process. Lett. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
A WLAN security management framework based on formal spatio-temporal RBAC model. |
Security and Communication Networks |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Antara Ain, Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay, Rajdeep Mukhopadhyay, John Gough |
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay |
Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta |
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhankar Mukherjee, Pallab Dasgupta |
Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
Policy Based Security Analysis in Enterprise Networks: A Formal Approach. |
IEEE Transactions on Network and Service Management |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Bounded delay timing analysis and power estimation using SAT. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyankar Ghosh, Pallab Dasgupta |
Detecting Ontological Conflicts in Protocols between Semantic Web Services |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, S. K. Panda, Siddhartha Mukhopadhyay |
A static verification approach for architectural integration of mixed-signal integrated circuits. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
A Spatio-Temporal Role-Based Access Control Model for Wireless LAN Security Policy Management. |
ICISTM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha |
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
power intent verification, formal verification, assertion |
| 1 | Padmalochan Bera, Soumya Maity, Soumya Kanti Ghosh, Pallab Dasgupta |
A Query based Formal Security Analysis Framework for Enterprise LAN. |
CIT |
2010 |
DBLP DOI BibTeX RDF |
Access Control, Formal Method, Network Security, Wireless LAN |
| 1 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
| 1 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Coverage Management with Inline Assertions and Formal Test Points. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Simulation, Verification, Coverage, Test Plan |
| 1 | Manoj G. Dixit, Pallab Dasgupta, S. Ramesh |
Taming the component timing: A CBD methodology for real-time embedded systems. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | P. V. Rajkumar, Soumya Kanti Ghosh, Pallab Dasgupta |
Concurrent Usage Control Implementation Verification Using the SPIN Model Checker. |
CNSA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Padmalochan Bera, Soumya Maity, Soumya Kanti Ghosh, Pallab Dasgupta |
A SAT Based Verification Framework for Wireless LAN Security Policy Management Supported by STRBAC Model. |
CNSA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough |
Instrumenting AMS assertion verification on commercial platforms. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion |
| 1 | Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti |
Design intent coverage revisited. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Design Intent Coverage |
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
Fault Analysis of Security Policy Implementations in Enterprise Networks. |
NetCoM |
2009 |
DBLP DOI BibTeX RDF |
Access Control List(ACL), SAT based verification, Network Security, LAN |
| 1 | Padmalochan Bera, Soumya Kanti Ghosh, Pallab Dasgupta |
Formal Verification of Security Policy Implementations in Enterprise Networks. |
ICISS |
2009 |
DBLP DOI BibTeX RDF |
Access control list (ACL), Formal Verification, Network security, Security Policy |
| 1 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Inline Assertions - Embedding Formal Properties in a Test Bench. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhankar Mukherjee, Antara Ain, S. K. Panda, Rajdeep Mukhopadhyay, Pallab Dasgupta |
A formal approach for specification-driven AMS behavioral model generation. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Auxiliary state machines + context-triggered properties in verification. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta |
Accelerating Assertion Coverage With Adaptive Testbenches. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Satisfiability Models for Maximum Transition Power. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan |
Cohesive Coverage Management for Simulation and Formal Property Verification. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan |
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. |
ATVA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Kausik Datta, Pallab Dasgupta |
CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications. |
ATVA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Event propagation for accurate circuit delay calculation using SAT. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Critical delay, event propagation, SAT |
| 1 | Bhaskar Pal, Arnab Sinha, Pallab Dasgupta, P. P. Chakrabarti, Kaushik De |
Hardware accelerated constrained random test generation. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
BUSpec: A framework for generation of verification aids for standard bus protocol specifications. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta |
Timing Analysis of Sequential Circuits Using Symbolic Event Propagation. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti |
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta |
Bounded Delay Timing Analysis Using Boolean Satisfiability. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni |
Design-Intent Coverage - A New Paradigm for Formal Property Verification. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Formal methods for checking realizability of coalitions in 3-party systems. |
MEMOCODE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta |
A Framework for Estimating Peak Power in Gate-Level Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta |
Test generation games from formal specifications. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
vacuity, test generation, realizability |
| 1 | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti |
Discovering the input assumptions in specification refinement coverage. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Samik Das, P. P. Chakrabarti, Pallab Dasgupta |
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti |
What lies between design intent coverage and model checking? |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti |
Synthesis of system verilog assertions. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta |
The open family of temporal logics: Annotating temporal operators with input constraints. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix |
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti |
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti |
SAT based solutions for consistency problems in formal property specifications for open systems. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
The power of first-order quantification over states in branching and linear time temporal logics. |
Inf. Process. Lett. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures. |
IWDC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
The BUSpec platform for automated generation of verification aids for standard bus protocols. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti |
Formal Verification of Modules under Real Time Environment Constraints. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan |
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix |
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni |
Formal verification coverage: computing the coverage gap between temporal specifications. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti |
A Branching Time Temporal Framework for Quantitative Reasoning. |
J. Autom. Reasoning |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti |
Open computation tree logic with fairness. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Arnab Dey, Sujoy Ghose, Wolfgang Bibel |
Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques. |
IEEE Trans. Knowl. Data Eng. |
2002 |
DBLP DOI BibTeX RDF |
logic programming, heuristic search, constraint optimization |
| 1 | Anindya C. Patthak, Indrajit Bhattacharya, Anirban Dasgupta, Pallab Dasgupta, P. P. Chakrabarti |
Quantified Computation Tree Logic. |
Inf. Process. Lett. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee |
Formal verification of module interfaces against real time specifications. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal verification, temporal logic |
| 1 | Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti |
Open Computation Tree Logic for Formal Verification of Modules. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan |
Min-max Computation Tree Logic. |
Artif. Intell. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti |
Abstraction of word-level linear arithmetic functions from bit-level component descriptions. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti |
Symbolic verification of Boolean constraints over partially specified functions. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti |
Abstractions for model checking of event timings. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti |
Model checking on timed-event structures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashanti Das, Dibyendu Das, Pallab Dasgupta |
Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems. |
HiPC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose |
Controlling State Explosion in Static Simulation by Selective Composition. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti |
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti |
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta |
Agreement under Faulty Interfaces. |
Inf. Process. Lett. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Dibyendu Das, Pallab Dasgupta, Prashanti Das |
A Heuristic for the Maximum Processor Requirement for Scheduling Layered Task Graphs with Coloring. |
J. Parallel Distrib. Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, A. K. Majumder, P. Bhattacharya |
V_THR: An Adaptive Load Balancing Algorithm. |
J. Parallel Distrib. Comput. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs. |
Inf. Process. Lett. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
Multiobjektive Heuristic Search in AND/OR Graphs. |
J. Algorithms |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
Searching Game Trees under a Partial Order. |
Artif. Intell. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
A New Competitive Algorithm for Agent Searching in Unknown Streets. |
FSTTCS |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
Utility of Pathmax in Partial Order Heuristic Search. |
Inf. Process. Lett. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening". |
Artif. Intell. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors. |
FSTTCS |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar |
Agent Searching in a Tree and the Optimality of Iterative Deepening. |
Artif. Intell. |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar |
Multiobjective Search in VLSI Design. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
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